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annotate gsm-fw/bsp/iq.h @ 990:2a867e5768e9

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fc-dspapidump fix: be independent of host byte order
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 12 Dec 2015 20:07:51 +0000
parents afceeeb2cba1
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : iq.h
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12
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13 Description : Interrupt header
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14
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15 Project : drivers
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16
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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18
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19 Version number : 1.13
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20
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21 Date and time : 01/30/01 10:22:22
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22
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23 Previous delta : 12/19/00 14:22:53
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24
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.iq.h
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26
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27 Sccs Id (SID) : '@(#) iq.h 1.13 01/30/01 10:22:22 '
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29
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30 *****************************************************************************/
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31
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32 #include "../include/config.h"
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33 #include "../include/sys_types.h"
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34
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35 // Hardware driver library build number
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36 #define IQ_BUILD 1
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37
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38 #define WS_MASK 0x001F
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39
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40 #if (CHIPSET == 4)
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41 #define IQ_NUM_INT 20
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42 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
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43 #define IQ_NUM_INT 25
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44 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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45 #define IQ_NUM_INT 21
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46 #elif (CHIPSET == 12)
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47 #define IQ_NUM_INT 32 // 2nd level interrupt handler is not considered here
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48 #else
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49 #define IQ_NUM_INT 16
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50 #endif
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51
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52
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53 #define IRQ 0
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54 #define FIQ 1
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55
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56 /*
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57 * Interrupt bit numbers
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58 */
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59 #define IQ_WATCHDOG 0
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60
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61 #define IQ_TIM1 1
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62 #define IQ_TIM2 2
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63 #define IQ_TSP 3
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64 #define IQ_FRAME 4
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65 #define IQ_PAGE 5
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66 #define IQ_SIM 6
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67 #define IQ_UART_IT 7
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68 #if (CHIPSET == 12)
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69 #define IQ_KEYBOARD 8
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70 #else
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71 #define IQ_ARMIO 8
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72 #endif
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73 #define IQ_RTC_TIMER 9
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74 #define IQ_RTC_ALARM 10
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75 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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76 #define IQ_TGSM 19
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77 #else
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78 #define IQ_TGSM 10
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79 #endif
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80 #define IQ_ULPD_GAUGING 11
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81 #define IQ_EXT 12
109
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82 #if ((CHIPSET == 10) || (CHIPSET == 11))
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83 #define IQ_API 15
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84 #endif // (CHIPSET == 10) || (CHIPSET == 11)
93
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85 #if (CHIPSET == 12)
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86 #define IQ_ARMIO 16
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87 #else
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88 #define IQ_SIM_CD 16
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89 #endif
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90
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91 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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92 #define IQ_UART_IRDA_IT 18
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93 #endif
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94
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95 #if (CHIPSET == 12)
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96 #define IQ_UART_MODEM2_IT 28
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97 #endif
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98 #define IQ_ICR 20
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99
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100 #if ((CHIPSET == 5) || (CHIPSET == 6))
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101 #define IQ_GEA_IT 24
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102 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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103 #define IQ_GEA_IT 20
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104 #endif
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105
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106 /**** JTAG ID ****/
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107 #define SATURN 0xB217
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108 #define HERCRAM 0xB268
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109 #define F731782 0xB2B5 // HERCROM OLD
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110 #define F731782B 0xB2B5 // HERCROM 1M REV B
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111 #define F731782A 0xB335 // HERCROM 1M REV A
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112 #define F731950 0xB334 // HERCROM 2M
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113 #if (CHIPSET == 4)
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114 #define F731787 0xB2AC // HERCRAM20G
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115 #endif
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116 #if ((CHIPSET == 5) || (CHIPSET == 6))
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117 #define F741709 0xB393 // HERCROM20G1
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118 #endif
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119 #if (CHIPSET == 9)
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120 #define F751681 0xB217 // HERCROM200C035
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121 #endif
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122 #if (CHIPSET == 12)
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123 #define F751997 0xB512 // HERCROM500G2C035
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124 #endif
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125
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126
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127 unsigned IQ_GetBuild(void);
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128 void IQ_SetupInterrupts(void);
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129 void IQ_Dummy(void);
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130 void IQ_TimerHandler(void); /* Watchdog timer */
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131 void IQ_TimerHandler1(void); /* timer 1 */
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132 void IQ_TimerHandler2(void); /* timer 2 */
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133 void IQ_FrameHandler(void); /* It Handler for TPU Frame IT NUCLEUS TICKS */
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134 void IQ_IcrHandler32(void); // 32-bit ICR interrupt handler
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135 void IQ_SetupInterruptEdge(unsigned short irq_num);
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136 void IQ_SetupInterruptLevel(unsigned short irq_num);
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137 void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag);
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138 void IQ_Unmask(unsigned irqNum);
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139 void IQ_Mask(unsigned irqNum);
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140 void IQ_MaskAll(void);
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141 /*
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142 * FreeCalypso change: our starting version had #if/#elif logic
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143 * selecting between declaring IQ_KeypadGPIOHandler() or IQ_KeypadHandler()
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144 * based on BOARD voodoo numbers.
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145 *
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146 * Given that the actual Calypso interrupt covers both GPIO and keypad
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147 * possibilities, let's always have an IQ_KeypadGPIOHandler() function
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148 * and put whatever per-target conditionals are needed inside.
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149 */
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150 void IQ_KeypadGPIOHandler (void);
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151 /* end of FC change */
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152 SYS_UWORD16 IQ_GetJtagId(void);
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153 SYS_UWORD16 IQ_GetDeviceVersion(void);
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154 SYS_BOOL IQ_RamBasedLead(void);
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155 SYS_UWORD16 IQ_GetRevision(void);
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156 void IQ_Gauging_Handler(void);
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157 void IQ_External(void);
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158 void IQ_Rtc_Handler(void);
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159 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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160 void IQ_RtcA_Handler(void);
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161 void IQ_GsmTim_Handler(void);
109
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162 void IQ_ApiHandler(void);
93
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163 #else
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164 void IQ_RtcA_GsmTim_Handler(void);
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165 #endif
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166 #if ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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167 // void IQ_GEA_Handler(void);
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168 #endif
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169
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170 #if (TI_PROFILER == 1)
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171 void IQ_InitLevel( SYS_UWORD16 inputInt,
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172 SYS_UWORD16 FIQ_nIRQ,
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173 SYS_UWORD16 priority,
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174 SYS_UWORD16 edge );
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175 #endif