FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/include/leo-based/fc-diffs @ 764:2d8cb1c85e01
sms_tlf.c compiles
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 12 Oct 2014 00:12:34 +0000 |
parents | 25a7fe25864c |
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rev | line source |
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530
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1 diff l1_const.h |
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2 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_const.h 2009-11-07 06:38:12.000000000 -0800 |
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3 +++ l1_const.h 2014-07-14 17:41:39.772709632 -0800 |
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4 @@ -18,11 +18,13 @@ |
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5 #else // Running ARM compiler. |
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6 #define FAR |
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7 #define EXIT exit(0) |
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8 + #undef stricmp // appease gcc |
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9 #define stricmp strcmp |
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10 #endif |
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11 |
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12 |
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13 #if (CODE_VERSION != SIMULATION) |
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14 + #undef NULL // appease gcc |
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15 #define NULL 0 |
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16 #endif |
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17 |
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18 @@ -1264,7 +1266,7 @@ |
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19 |
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20 // "d_ctrl_abb" bits positions for conditionnal loading of abb registers. |
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21 #define B_RAMP 0 |
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22 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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23 +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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24 #define B_BULRAMPDEL 3 // Note: this name is changed |
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25 #define B_BULRAMPDEL2 2 // Note: this name is changed |
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26 #define B_BULRAMPDEL_BIS 9 |
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27 diff l1_ctl.h |
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28 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_ctl.h 2009-11-07 06:38:12.000000000 -0800 |
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29 +++ l1_ctl.h 2013-11-16 20:27:53.000000000 -0800 |
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30 @@ -50,10 +50,8 @@ |
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31 #define ALGO_AFC_KALMAN_PREDICTOR 3 // Kalman filter + rgap predictor |
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32 #endif |
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33 |
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34 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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35 +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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36 // clipping related to AFC DAC linearity range |
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37 #define C_max_step 32000 // 4000 * 2**3 |
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38 #define C_min_step -32000 // -4000 * 2**3 |
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39 #endif |
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40 - |
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41 - |
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42 diff l1_defty.h |
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43 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_defty.h 2009-11-07 06:38:12.000000000 -0800 |
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44 +++ l1_defty.h 2014-07-10 07:19:36.915001165 -0800 |
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45 @@ -7,7 +7,7 @@ |
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46 * |
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47 ************* Revision Controle System Header *************/ |
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48 #if(L1_DYN_DSP_DWNLD == 1) |
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49 - #include "l1_dyn_dwl_defty.h" |
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50 + #include "../dyn_dwl_include/l1_dyn_dwl_defty.h" |
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51 #endif |
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52 |
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53 typedef struct |
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54 @@ -421,7 +421,7 @@ |
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55 // bit [12.13] -> b_tch_loop, tch loops A/B/C. |
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56 API hole; // (10) unused hole. |
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57 |
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58 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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59 +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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60 API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send. |
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61 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB |
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62 // bit [1.2] -> unused |
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63 @@ -552,9 +552,9 @@ |
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64 API d_dai_onoff; |
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65 API d_auxdac; |
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66 |
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67 - #if (ANLG_FAM == 1) |
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68 + #if (ANALOG == 1) |
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69 API d_vbctrl; |
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70 - #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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71 + #elif ((ANALOG == 2) || (ANALOG == 3)) |
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72 API d_vbctrl1; |
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73 #endif |
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74 |
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75 @@ -660,7 +660,7 @@ |
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76 API d_gea_mode_ovly; |
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77 API a_gea_kc_ovly[4]; |
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78 |
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79 -#if (ANLG_FAM == 3) |
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80 +#if (ANALOG == 3) |
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81 // SYREN specific registers |
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82 API d_vbpop; |
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83 API d_vau_delay_init; |
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84 @@ -669,7 +669,7 @@ |
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85 API d_vaus_vol; |
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86 API d_vaud_pll; |
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87 API d_hole3_ndb[1]; |
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88 -#elif ((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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89 +#elif ((ANALOG == 1) || (ANALOG == 2)) |
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90 |
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91 API d_hole3_ndb[7]; |
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92 |
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93 @@ -896,9 +896,9 @@ |
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94 API d_dai_onoff; |
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95 API d_auxdac; |
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96 |
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97 - #if (ANLG_FAM == 1) |
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98 + #if (ANALOG == 1) |
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99 API d_vbctrl; |
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100 - #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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101 + #elif ((ANALOG == 2) || (ANALOG == 3)) |
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102 API d_vbctrl1; |
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103 #endif |
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104 |
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105 @@ -1157,7 +1157,7 @@ |
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106 // bit [2] -> b_dtx. |
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107 |
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108 // OMEGA...........................(MCU -> DSP). |
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109 - #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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110 + #if ((ANALOG == 1) || (ANALOG == 2)) |
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111 API a_ramp[16]; |
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112 #if (MELODY_E1) |
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113 API d_melo_osc_used; |
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114 @@ -1215,9 +1215,9 @@ |
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115 API d_dai_onoff; |
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116 API d_auxdac; |
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117 |
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118 - #if (ANLG_FAM == 1) |
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119 + #if (ANALOG == 1) |
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120 API d_vbctrl; |
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121 - #elif (ANLG_FAM == 2) |
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122 + #elif (ANALOG == 2) |
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123 API d_vbctrl1; |
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124 #endif |
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125 |
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126 @@ -1387,7 +1387,7 @@ |
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127 |
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128 // OMEGA...........................(MCU -> DSP). |
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129 |
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130 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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131 +#if ((ANALOG == 1) || (ANALOG == 2)) |
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132 API a_ramp[16]; |
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133 #if (MELODY_E1) |
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134 API d_melo_osc_used; |
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135 @@ -1443,9 +1443,9 @@ |
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136 API d_bulqoff; |
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137 API d_dai_onoff; |
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138 API d_auxdac; |
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139 - #if (ANLG_FAM == 1) |
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140 + #if (ANALOG == 1) |
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141 API d_vbctrl; |
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142 - #elif (ANLG_FAM == 2) |
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143 + #elif (ANALOG == 2) |
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144 API d_vbctrl1; |
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145 #endif |
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146 API d_bbctrl; |
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147 @@ -2834,7 +2834,7 @@ |
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148 BOOL dco_enabled; |
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149 #endif |
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150 |
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151 - #if (ANLG_FAM == 1) |
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152 + #if (ANALOG == 1) |
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153 UWORD16 debug1; |
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154 UWORD16 afcctladd; |
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155 UWORD16 vbuctrl; |
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156 @@ -2848,7 +2848,7 @@ |
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157 UWORD16 vbctrl; |
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158 UWORD16 apcdel1; |
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159 #endif |
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160 - #if (ANLG_FAM == 2) |
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161 + #if (ANALOG == 2) |
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162 UWORD16 debug1; |
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163 UWORD16 afcctladd; |
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164 UWORD16 vbuctrl; |
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165 @@ -2865,7 +2865,7 @@ |
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166 UWORD16 apcdel1; |
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167 UWORD16 apcdel2; |
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168 #endif |
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169 - #if (ANLG_FAM == 3) |
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170 + #if (ANALOG == 3) |
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171 UWORD16 debug1; |
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172 UWORD16 afcctladd; |
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173 UWORD16 vbuctrl; |
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174 diff l1_macro.h |
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175 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_macro.h 2009-11-07 06:38:12.000000000 -0800 |
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176 +++ l1_macro.h 2013-11-16 12:55:51.000000000 -0800 |
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177 @@ -10,7 +10,7 @@ |
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178 #include "l1_confg.h" |
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179 |
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180 #if(L1_DYN_DSP_DWNLD == 1) |
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181 - #include "l1_dyn_dwl_const.h" |
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182 + #include "../dyn_dwl_include/l1_dyn_dwl_const.h" |
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183 #endif |
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184 |
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185 #if (TRACE_TYPE==5) && NUCLEUS_TRACE |
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186 diff l1_proto.h |
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187 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_proto.h 2009-11-07 06:38:12.000000000 -0800 |
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188 +++ l1_proto.h 2014-07-10 07:18:34.489000271 -0800 |
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189 @@ -134,7 +134,7 @@ |
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190 /* prototypes of L1_FUNC functions */ |
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191 /**************************************/ |
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192 void dsp_power_on (void); |
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193 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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194 +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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195 void l1_abb_power_on (void); |
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196 #endif |
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197 void tpu_init (void); |
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198 @@ -517,7 +517,7 @@ |
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199 WORD8 l1ctl_encode_delta1 (UWORD16 radio_freq); |
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200 WORD8 l1ctl_encode_delta2 (UWORD16 radio_freq); |
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201 void Cust_get_ramp_tab (API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); |
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202 -#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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203 +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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204 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq); |
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205 #endif |
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206 |
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207 diff l1_time.h |
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208 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_time.h 2009-11-07 06:38:12.000000000 -0800 |
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209 +++ l1_time.h 2014-07-10 07:18:53.908001527 -0800 |
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210 @@ -140,7 +140,7 @@ |
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211 #if (CODE_VERSION==SIMULATION) |
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212 #define TULSET_DURATION ( 16L ) // Uplink power on setup time |
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213 #define BULRUDEL_DURATION ( 2L ) |
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214 - #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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215 + #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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216 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit |
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217 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB) |
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218 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay |
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219 diff l1_trace.h |
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220 --- ../../../../leo2moko/chipsetsw/layer1/include/l1_trace.h 2009-11-07 06:38:12.000000000 -0800 |
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221 +++ l1_trace.h 2014-07-14 23:32:39.826002442 -0800 |
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222 @@ -11,7 +11,7 @@ |
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223 #ifndef __L1_TRACE_H__ |
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224 #define __L1_TRACE_H__ |
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225 |
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226 -#include "rvt_gen.h" |
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227 +#include "../../riviera/rvt/rvt_gen.h" |
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228 #include <string.h> |
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229 |
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230 #if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1)) |