FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/niq32.c @ 653:31d82d090499
gsm-fw/cdg: should be ready to run ccdgen
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Thu, 25 Sep 2014 09:00:04 +0000 |
parents | 7310ce904148 |
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1 /****************************************************************************** |
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 |
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 product is protected under copyright law and trade secret law as an |
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
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8 rights reserved. |
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9 |
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10 |
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11 Filename : niq32.c |
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12 |
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13 Description : Nucleus IQ initializations |
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14 |
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15 Project : Drivers |
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16 |
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17 Author : proussel@ti.com Patrick Roussel. |
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18 |
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19 Version number : 1.25 |
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20 |
112
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21 Date : 08/22/03 |
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22 |
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23 Previous delta : 12/19/00 14:24:51 |
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24 |
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25 *******************************************************************************/ |
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26 |
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27 #include "../include/config.h" |
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28 #include "../include/sys_types.h" |
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29 |
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30 #include "inth.h" |
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31 #include "mem.h" |
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32 #include "iq.h" |
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33 #include "ulpd.h" |
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34 #include "armio.h" |
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35 |
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36 #include "../serial/serialswitch.h" |
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37 #include "rtc/rtc_config.h" |
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38 |
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39 #if CONFIG_INCLUDE_SIM |
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40 #include "sim.h" |
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41 #endif |
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42 |
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43 #if 0 |
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44 |
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45 /* original maze of includes */ |
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46 |
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47 #if(OP_L1_STANDALONE == 0) |
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48 #include "debug.cfg" |
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49 #include "rv/rv_defined_swe.h" |
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50 #include "rtc/board/rtc_config.h" |
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51 #else |
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52 #include "l1_macro.h" |
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53 #include "l1_confg.h" |
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54 #endif |
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55 |
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56 #if(OP_L1_STANDALONE == 0) |
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57 #include "swconfig.cfg" |
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58 #ifdef BLUETOOTH_INCLUDED |
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59 #include "btemobile.cfg" |
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60 #ifdef BT_CLK_REQ_INT |
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61 #include "board/bth_drv.h" |
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62 #endif |
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63 #endif |
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64 #endif |
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65 |
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66 |
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67 #if(L1_DYN_DSP_DWNLD == 1) |
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68 #include "l1_api_hisr.h" |
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69 #endif |
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70 |
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71 #if (OP_L1_STANDALONE == 0) |
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72 #include "main/sys_types.h" |
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73 #else |
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74 #include "sys_types.h" |
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75 #endif |
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76 |
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77 #if (CHIPSET == 12) |
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78 #include "sys_inth.h" |
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79 #else |
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80 #include "inth/inth.h" |
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81 #include "memif/mem.h" |
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82 #if (OP_L1_STANDALONE == 1) |
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83 #include "serialswitch_core.h" |
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84 #else |
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85 #include "uart/serialswitch.h" |
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86 #endif |
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87 |
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88 #if (OP_L1_STANDALONE == 0) |
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89 #include "sim/sim.h" |
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90 #endif |
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91 #endif |
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92 |
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93 #include "abb/abb_core_inth.h" // for External Interrupt |
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94 #define IQ_H |
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95 #include "inth/iq.h" |
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96 #include "ulpd/ulpd.h" |
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97 #if (BOARD == 34) |
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98 #include "csmi/csmi.h" |
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99 #endif |
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100 |
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101 #if (defined RVM_DAR_SWE) && (defined _GSM) |
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102 extern void dar_watchdog_reset(void); |
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103 #endif |
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104 |
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105 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45)) |
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106 #include "armio/armio.h" |
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107 #if (OP_L1_STANDALONE == 0) |
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108 #include "uart/uartfax.h" |
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109 #endif |
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110 #endif |
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111 |
113
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112 /* end of original include maze */ |
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113 #endif |
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114 |
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115 /* External declaration */ |
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116 extern void GAUGING_Handler(void); |
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117 extern void TMT_Timer_Interrupt(void); |
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118 #if 0 //(OP_L1_STANDALONE == 1) |
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119 extern void TM_Timer1Handler(void); |
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120 #endif |
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121 extern void kpd_key_handler(void); |
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122 extern void TP_FrameIntHandler(void); |
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123 |
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124 #if 1 //(OP_L1_STANDALONE == 0) |
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125 #if (defined RVM_MPM_SWE) |
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126 extern void MPM_InterruptHandler(void); |
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127 #endif |
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128 |
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129 #if (TI_PROFILER == 1) |
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130 extern void ti_profiler_tdma_action(void); |
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131 #endif |
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132 |
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133 #if(RF_FAM==35) |
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134 extern void TSP_RxHandler(void); |
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135 #endif |
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136 |
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137 extern void RTC_GaugingHandler(void); |
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138 extern void RTC_ItTimerHandle(void); |
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139 extern void RTC_ItAlarmHandle(void); |
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140 #endif |
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141 |
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142 /* Global variables */ |
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143 unsigned IQ_TimerCount1; /* Used to check if timer is incrementing */ |
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144 unsigned IQ_TimerCount2; /* Used to check if timer is incrementing */ |
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145 unsigned IQ_TimerCount; /* Used to check if timer is incrementing */ |
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146 unsigned IQ_DummyCount; /* Used to check if dummy IT */ |
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147 unsigned IQ_FrameCount; /* Used to check if Frame IT TPU*/ |
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148 unsigned IQ_GsmTimerCount; /* Used to check if GSM Timer IT */ |
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149 |
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150 /*--------------------------------------------------------------*/ |
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151 /* irqHandlers */ |
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152 /*--------------------------------------------------------------*/ |
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153 /* Parameters :none */ |
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154 /* Return : none */ |
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155 /* Functionality : Table of interrupt handlers */ |
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156 /* These MUST be 32-bit entries */ |
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157 /*--------------------------------------------------------------*/ |
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158 |
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159 SYS_FUNC irqHandlers[IQ_NUM_INT] = |
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160 { |
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161 IQ_TimerHandler, /* Watchdog timer */ |
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162 IQ_TimerHandler1, /* timer 1 */ |
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163 IQ_TimerHandler2, /* timer 2 */ |
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164 IQ_Dummy, /* AIRQ 3 */ |
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165 IQ_FrameHandler, /* TPU Frame It AIRQ 4 */ |
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166 IQ_Dummy, /* AIRQ 5 */ |
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167 #if CONFIG_INCLUDE_SIM //(OP_L1_STANDALONE == 0) |
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168 SIM_IntHandler, /* AIRQ 6 */ |
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169 #else |
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170 IQ_Dummy, /* AIRQ 6 */ |
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171 #endif |
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172 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
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173 SER_uart_handler, /* AIRQ 7 */ |
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174 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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175 SER_uart_modem_handler, /* AIRQ 7 */ |
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176 #endif |
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177 #if 1 //((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) |
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178 // CC test 0316 |
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179 IQ_KeypadGPIOHandler, /* AIRQ 8 */ |
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180 // end |
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181 #else |
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182 IQ_KeypadHandler, /* AIRQ 8 */ |
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183 #endif |
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184 IQ_Rtc_Handler, /* AIRQ 9 RTC Timer*/ |
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185 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
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186 IQ_RtcA_GsmTim_Handler, /* AIRQ 10 RTC ALARM OR ULPD GSM TIMER*/ |
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187 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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188 IQ_RtcA_Handler, /* AIRQ 10 RTC ALARM */ |
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189 #endif |
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190 IQ_Gauging_Handler, /* AIRQ 11 ULPD GAUGING */ |
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191 IQ_External, /* AIRQ 12 */ |
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192 IQ_Dummy, /* AIRQ 13 */ |
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193 IQ_Dummy, /* DMA interrupt */ |
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194 #if (CHIPSET == 4) |
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195 IQ_Dummy, /* LEAD */ |
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196 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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197 IQ_Dummy, /* External fast interrupt */ |
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198 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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199 IQ_GsmTim_Handler /* ULPD GSM timer */ |
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200 #elif ((CHIPSET == 5) || (CHIPSET == 6)) |
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201 IQ_Dummy, /* LEAD */ |
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202 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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203 IQ_Dummy, /* External fast interrupt */ |
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204 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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205 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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206 #if (BOARD == 34) |
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207 IQ_IcrHandler32, |
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208 #else |
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209 IQ_Dummy, /* Not mapped interrupt */ |
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210 #endif |
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211 IQ_Dummy, /* Not mapped interrupt */ |
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212 IQ_Dummy, /* Not mapped interrupt */ |
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213 IQ_Dummy, /* Not mapped interrupt */ |
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214 IQ_Dummy /* GEA interrupt */ |
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215 #elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
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216 #if 0 //(L1_DYN_DSP_DWNLD == 1) |
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217 IQ_ApiHandler, /* LEAD */ |
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218 #else |
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219 IQ_Dummy, /* LEAD */ |
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220 #endif |
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221 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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222 IQ_Dummy, /* External fast interrupt */ |
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223 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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224 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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225 IQ_Dummy /* GEA interrupt */ |
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226 #elif (CHIPSET == 9) |
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227 IQ_Dummy, /* LEAD */ |
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228 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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229 IQ_Dummy, /* External fast interrupt */ |
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230 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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231 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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232 IQ_Dummy, /* Not mapped interrupt */ |
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233 IQ_Dummy, /* Not mapped interrupt */ |
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234 IQ_Dummy, /* Not mapped interrupt */ |
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235 IQ_Dummy, /* Not mapped interrupt */ |
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236 IQ_Dummy /* Reserved */ |
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237 #else |
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238 IQ_Dummy /* LEAD */ |
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239 #endif |
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240 }; |
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241 |
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242 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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243 /*--------------------------------------------------------------*/ |
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244 /* fiqHandlers */ |
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245 /*--------------------------------------------------------------*/ |
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246 /* Parameters :none */ |
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247 /* Return :none */ |
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248 /* Functionality : Table of interrupt handlers */ |
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249 /* These MUST be 32-bit entries */ |
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250 /*--------------------------------------------------------------*/ |
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251 |
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252 SYS_FUNC fiqHandlers[IQ_NUM_INT] = |
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253 { |
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254 IQ_Dummy, /* Watchdog timer */ |
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255 IQ_Dummy, /* timer 1 */ |
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256 IQ_Dummy, /* timer 2 */ |
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257 #if ((OP_L1_STANDALONE == 0) && (RF_FAM == 35)) |
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258 TSP_RxHandler, /* 3 TSP */ |
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259 #else |
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260 IQ_Dummy, /* AIRQ 3 */ |
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261 #endif |
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262 IQ_Dummy, /* TPU Frame It AIRQ 4 */ |
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263 IQ_Dummy, /* AIRQ 5 */ |
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264 IQ_Dummy, /* AIRQ 6 */ |
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265 IQ_Dummy, /* AIRQ 7 */ |
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266 IQ_Dummy, /* AIRQ 8 */ |
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267 IQ_Dummy, /* AIRQ 9 RTC Timer */ |
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268 IQ_Dummy, /* AIRQ 10 RTC ALARM */ |
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269 IQ_Dummy, /* AIRQ 11 ULPD GAUGING */ |
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270 IQ_Dummy, /* AIRQ 12 */ |
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271 IQ_Dummy, /* AIRQ 13 Spi Tx Rx interrupt */ |
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272 IQ_Dummy, /* DMA interrupt */ |
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273 IQ_Dummy, /* LEAD */ |
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274 #if CONFIG_INCLUDE_SIM //(OP_L1_STANDALONE == 0) |
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275 SIM_CD_IntHandler, /* SIM card-detect fast interrupt */ |
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276 #else |
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277 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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278 #endif |
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279 IQ_Dummy, /* External fast interrupt */ |
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280 IQ_Dummy, /* UART_IRDA interrupt */ |
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281 #if (CHIPSET == 4) |
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282 IQ_Dummy /* ULPD GSM timer */ |
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283 #elif ((CHIPSET == 5) || (CHIPSET == 6)) |
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284 IQ_Dummy, /* ULPD GSM timer */ |
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285 IQ_Dummy, /* Not mapped interrupt */ |
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286 IQ_Dummy, /* Not mapped interrupt */ |
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287 IQ_Dummy, /* Not mapped interrupt */ |
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288 IQ_Dummy, /* Not mapped interrupt */ |
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289 IQ_Dummy /* GEA interrupt */ |
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290 #elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
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291 IQ_Dummy, /* ULPD GSM timer */ |
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292 IQ_Dummy /* GEA timer */ |
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293 #elif (CHIPSET == 9) |
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294 IQ_Dummy, /* ULPD GSM timer */ |
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295 IQ_Dummy, /* Not mapped interrupt */ |
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296 IQ_Dummy, /* Not mapped interrupt */ |
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297 IQ_Dummy, /* Not mapped interrupt */ |
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298 IQ_Dummy, /* Not mapped interrupt */ |
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299 IQ_Dummy /* Reserved */ |
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300 #endif |
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301 }; |
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302 #endif |
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303 |
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304 /*--------------------------------------------------------------*/ |
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305 /* IQ_Gauging_Handler */ |
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306 /*--------------------------------------------------------------*/ |
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307 /* Parameters :none */ |
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308 /* Return : none */ |
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309 /* Functionality : Handle unused interrupts */ |
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310 /*--------------------------------------------------------------*/ |
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311 void IQ_Gauging_Handler(void) |
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312 { |
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313 #if CONFIG_INCLUDE_L1 |
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314 GAUGING_Handler(); |
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315 #if CONFIG_GSM |
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316 RTC_GaugingHandler(); |
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317 #endif |
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318 #endif |
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319 } |
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320 |
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321 |
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322 /*--------------------------------------------------------------*/ |
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323 /* IQ_External */ |
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324 /*--------------------------------------------------------------*/ |
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325 /* Parameters : none */ |
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326 /* Return : none */ |
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327 /* Functionality : Handle External IRQ mapped on ABB. */ |
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328 /*--------------------------------------------------------------*/ |
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329 void IQ_External(void) |
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330 { |
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331 #if (CHIPSET == 12) |
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332 // Mask external interrupt 12 |
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333 F_INTH_DISABLE_ONE_IT(C_INTH_ABB_IRQ_IT); |
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334 #else |
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335 // Mask external interrupt 12 |
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336 IQ_Mask(IQ_EXT); |
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337 #endif |
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338 |
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339 // The external IRQ is mapped on the ABB interrupt. |
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340 // The associated HISR ABB_Hisr is activated on reception on the external IRQ. |
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341 #if CONFIG_INCLUDE_L1 |
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342 if(Activate_ABB_HISR()) |
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343 { |
112
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344 #if (CHIPSET == 12) |
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345 F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); |
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346 #else |
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347 // Mask external interrupt 12 |
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348 IQ_Unmask(IQ_EXT); |
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349 #endif |
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350 } |
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351 #endif |
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352 } |
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353 |
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354 /*--------------------------------------------------------------*/ |
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355 /* IQ_Dummy */ |
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356 /*--------------------------------------------------------------*/ |
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357 /* Parameters :none */ |
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358 /* Return : none */ |
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359 /* Functionality : Handle unused interrupts */ |
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360 /*--------------------------------------------------------------*/ |
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361 void IQ_Dummy(void) |
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362 { |
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363 IQ_DummyCount++; |
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364 } |
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365 |
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366 /*--------------------------------------------------------------*/ |
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367 /* IQ_RTCHandler */ |
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368 /*--------------------------------------------------------------*/ |
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369 /* Parameters :none */ |
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370 /* Return : none */ |
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371 /* Functionality : Handle RTC Time interrupts */ |
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372 /*--------------------------------------------------------------*/ |
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373 |
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374 void IQ_Rtc_Handler(void) |
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375 { |
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376 #if CONFIG_GSM //(OP_L1_STANDALONE == 0) |
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377 RTC_ItTimerHandle(); |
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378 #endif |
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379 } |
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380 |
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381 /*--------------------------------------------------------------*/ |
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382 /* IQ_RtcA_GsmTim_Handler */ |
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383 /*--------------------------------------------------------------*/ |
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384 /* Parameters :none */ |
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385 /* Return : none */ |
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386 /* Functionality : Handle RTC ALARM or GAUGING interrupts */ |
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387 /*--------------------------------------------------------------*/ |
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388 |
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389 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
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390 void IQ_RtcA_Handler(void) |
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391 { |
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392 #if 1 //(OP_L1_STANDALONE == 0) |
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393 /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT */ |
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394 if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM ) |
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395 RTC_ItAlarmHandle(); |
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396 #endif |
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397 } |
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398 |
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399 void IQ_GsmTim_Handler(void) |
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400 { |
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401 |
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402 if ( (* (SYS_UWORD16 *) ULPD_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM ) |
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403 { |
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404 // it is GSM Timer it..... |
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405 IQ_GsmTimerCount++; |
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406 } |
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407 } |
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408 #else |
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409 void IQ_RtcA_GsmTim_Handler(void) |
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410 { |
112
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411 #if (OP_L1_STANDALONE == 0) |
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412 if ( (* (SYS_UWORD16 *) ULPD_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM ) |
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413 { |
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414 // it is GSM Timer it..... |
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415 IQ_GsmTimerCount++; |
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416 } |
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417 else |
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418 { |
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419 /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT */ |
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420 if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM ) |
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421 RTC_ItAlarmHandle(); |
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422 } |
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423 #endif |
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424 } |
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425 #endif |
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426 |
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427 /*--------------------------------------------------------------*/ |
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428 /* IQ_TimerHandler */ |
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429 /*--------------------------------------------------------------*/ |
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430 /* Parameters :none */ |
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431 /* Return : none */ |
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432 /* Functionality : Handle Timer interrupts */ |
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433 /*--------------------------------------------------------------*/ |
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434 void IQ_TimerHandler(void) |
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435 { |
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436 IQ_TimerCount++; |
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437 TMT_Timer_Interrupt(); |
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438 #if 0 //(defined RVM_DAR_SWE) && (defined _GSM) |
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439 dar_watchdog_reset(); |
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440 #endif |
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441 } |
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442 |
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443 /*--------------------------------------------------------------*/ |
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444 /* IQ_FramerHandler */ |
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445 /*--------------------------------------------------------------*/ |
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446 /* Parameters :none */ |
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447 /* Return : none */ |
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448 /* Functionality : Handle Timer interrupts */ |
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449 /*--------------------------------------------------------------*/ |
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450 void IQ_FrameHandler(void) |
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451 { |
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452 IQ_FrameCount++; |
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453 TMT_Timer_Interrupt(); |
601
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454 #if CONFIG_INCLUDE_L1 |
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455 TP_FrameIntHandler(); |
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456 #endif |
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457 #if (OP_L1_STANDALONE == 0) |
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458 #if (TI_PROFILER == 1) |
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459 // TDMA treatment for profiling buffer |
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460 ti_profiler_tdma_action(); |
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461 #endif |
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462 #endif |
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463 } |
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464 |
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465 /*--------------------------------------------------------------*/ |
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466 /* IQ_TimerHandler1 */ |
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467 /*--------------------------------------------------------------*/ |
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468 /* Parameters :none */ |
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469 /* Return : none */ |
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470 /* Functionality : Handle Timer 1 interrupts */ |
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471 /*--------------------------------------------------------------*/ |
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472 void IQ_TimerHandler1(void) |
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473 { |
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474 IQ_TimerCount1++; |
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475 #if (OP_L1_STANDALONE == 1) |
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476 TM_Timer1Handler(); |
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477 #endif |
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478 } |
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479 |
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480 /*--------------------------------------------------------------*/ |
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481 /* IQ_TimerHandler2 */ |
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482 /*--------------------------------------------------------------*/ |
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483 /* Parameters :none */ |
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484 /* Return : none */ |
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485 /* Functionality : Handle Timer 2 interrupts */ |
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486 /*--------------------------------------------------------------*/ |
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487 void IQ_TimerHandler2(void) |
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488 { |
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489 IQ_TimerCount2++; |
525
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490 #if !CONFIG_INCLUDE_L1 |
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491 TMT_Timer_Interrupt(); |
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492 #endif |
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493 } |
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494 |
113
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495 #if 0 //(L1_DYN_DSP_DWNLD == 1) |
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496 /*-------------------------------------------------------*/ |
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497 /* IQ_ApiHandler() */ |
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498 /*-------------------------------------------------------*/ |
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499 /* Parameters : none */ |
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500 /* Return : none */ |
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501 /* Functionality : API int management */ |
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502 /*-------------------------------------------------------*/ |
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503 void IQ_ApiHandler(void) |
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504 { |
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505 l1_api_handler(); |
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506 } /* IQ_ApiHandler() */ |
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507 #endif |
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508 |
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509 |
93
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510 /*--------------------------------------------------------------*/ |
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511 /* IQ_IRQ_isr */ |
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512 /*--------------------------------------------------------------*/ |
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513 /* Parameters :none */ |
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514 /* Return : none */ |
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515 /* Functionality : HHandle IRQ interrupts */ |
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516 /*--------------------------------------------------------------*/ |
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517 void IQ_IRQ_isr(void) |
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518 { |
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519 irqHandlers[((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM)](); /* ACK IT */ |
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520 * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_IRQ); /* valid next IRQ */ |
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521 } |
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522 |
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523 /*--------------------------------------------------------------*/ |
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524 /* IQ_FIQ_isr */ |
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525 /*--------------------------------------------------------------*/ |
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526 /* Parameters :none */ |
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527 /* Return : none */ |
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528 /* Functionality : Handle FIQ interrupts */ |
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529 /*--------------------------------------------------------------*/ |
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530 void IQ_FIQ_isr(void) |
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531 { |
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532 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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533 fiqHandlers[((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)](); /* ACK IT */ |
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534 #endif |
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535 * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_FIQ); /* valid next FIQ */ |
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536 } |
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537 |
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538 /*--------------------------------------------------------------*/ |
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539 /* IQ_KeypadGPIOHandler */ |
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540 /*--------------------------------------------------------------*/ |
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541 /* Parameters : none */ |
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542 /* Return : none */ |
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543 /* Functionality : Handle keypad and GPIO interrupts */ |
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544 /*--------------------------------------------------------------*/ |
112
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545 // CC test 0316 |
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546 //#include "rvm/rvm_use_id_list.h" |
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547 //#include "rvf/rvf_api.h" |
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548 //static char debug_buffer[50]; |
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549 // end |
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550 |
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551 void IQ_KeypadGPIOHandler(void) |
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552 { |
112
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553 |
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554 #if 0 //(OP_L1_STANDALONE == 0) |
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555 /* |
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556 * GPIO interrupt must be checked before the keypad interrupt. The GPIO |
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557 * status bit is reset when the register is read. |
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558 */ |
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559 |
112
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560 if (AI_CheckITSource (ARMIO_GPIO_INT)) |
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561 |
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562 // CC test 0315 |
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563 { |
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564 AI_MaskIT (ARMIO_MASKIT_GPIO); |
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565 //sprintf(debug_buffer, "GPIO_Interrupt"); |
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566 //rvf_send_trace(debug_buffer, 40, NULL_PARAM, RV_TRACE_LEVEL_ERROR, RVT_USE_ID); |
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567 AI_UnmaskIT(ARMIO_MASKIT_GPIO); //0x0002 |
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568 // end |
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569 /* |
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570 #ifdef RVM_MPM_SWE |
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571 // check if the SWE has been started |
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572 MPM_InterruptHandler (); |
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573 #elif BT_CLK_REQ_INT |
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574 |
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575 BT_DRV_ClkReqInterruptHandler( ); |
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576 #else |
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577 UAF_DTRInterruptHandler (); |
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578 #endif |
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579 */ |
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580 } |
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581 if (AI_CheckITSource (ARMIO_KEYPAD_INT)) |
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582 { |
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583 // CC test 0316 |
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584 //sprintf(debug_buffer, "Key_Interrupt"); |
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585 //rvf_send_trace(debug_buffer, 40, NULL_PARAM, RV_TRACE_LEVEL_ERROR, RVT_USE_ID); |
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586 // end |
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587 kpd_key_handler (); |
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588 } |
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589 |
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590 #endif |
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591 } |