freecalypso-sw: gsm-fw/riviera/init/create

annotate gsm-fw/riviera/init/create_RVtasks.c @ 884:353daaa6014d

gsm-fw/gpf/conf/gsmcomp.c: increased max partition in the voice-only config The code we got from TCS211 had the maximum prim pool partition size set to 900 bytes in the voice-only config (no FAX_AND_DATA, no GPRS) and to 1600 bytes in every other config. As it turns out, this "minimized" config breaks when the AT command interface is used with %CPI enabled, as the responsible code in ATI does an ACI_MALLOC of 1012 bytes. TI may have considered this case to be unsupported usage (perhaps they didn't care about the combination of a voice-only PS with AT command control), but we do want this use case to work without crashing. Solution: I made the largest prim pool the same as it is with FAX_AND_DATA: 3 partitions of 1600 bytes.

author	Space Falcon <falcon@ivan.Harhan.ORG>
date	Sat, 27 Jun 2015 07:31:30 +0000
parents	60afcd233b04
children

rev	line source
168 60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	1 /******************************************************************************
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	2 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	3 * Name create_RVtasks.c *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	4 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	5 * Function this file contains functions allowing tasks creation in *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	6 * the Riviera environment *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	7 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	8 * Version 0.1 *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	9 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	10 * Date Modification *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	11 * ------------------------------------ *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	12 * 03 August 2000 Create *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	13 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	14 * Author Pascal Puel *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	15 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	16 * (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	17 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	18 * -------------------------------------------------------------------------- *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	19 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	20 * History: *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	21 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	22 * 10/18/2001 - Updated for R2D by Christophe Favergeon *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	23 * 08/28/2002 - Clean-Up by Gerard Cauvy *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	24 * *
60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	25 *****************************************************************************/
129 7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	26
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	27 #include "../../include/config.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	28
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	29 #include "../rv/rv_general.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	30 #include "../rvf/rvf_api.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	31 #include "../rvm/rvm_api.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	32 #include "../rvm/rvm_use_id_list.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	33 #include "../rvt/rvt_gen.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	34
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	35 #if 0
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	36 //sys_types.h is necessary for function prototypes in buzzer.h
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	37 #include "sys_types.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	38 #include "buzzer/buzzer.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	39 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	40
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	41 #include "../rv/rv_defined_swe.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	42
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	43 #if 0 //#ifndef _WINDOWS
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	44 # include "power/power.h"
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	45 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	46
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	47 #include <stdio.h>
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	48 #include <string.h>
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	49
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	50 #define START_TASK_ID (MAX_RVF_TASKS-1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	51 #define RV_START_TASK_PRIO (249)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	52
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	53 T_RVT_USER_ID rv_trace_user_id = 0xff;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	54 T_RVT_USER_ID etm_trace_user_id;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	55
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	56 extern void etm_receive(unsigned char *inbuf, unsigned short size);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	57
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	58 #ifdef MIXED_TRACE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	59 T_RVT_USER_ID l23_trace_user_id;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	60 extern void ext_processExtInput (T_RVT_BUFFER, UINT16);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	61 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	62
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	63 #ifdef RVM_RNET_BR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	64 T_RVT_USER_ID rnet_trace_user_id;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	65 extern void rnet_receive (UINT8 *inbuf, UINT16 size);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	66 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	67
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	68 #if (TEST==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	69
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	70 // The name that uniquely identifies the Memory Bank MUST be
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	71 // 'TEST1', whereas it might be used by some other software
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	72 // entity for testing purpose.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	73 #define RVTEST_MENU_MB_NAME ("TEST1")
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	74
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	75 // Memory requirements.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	76 #define RVTEST_MENU_MB_SIZE (5000)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	77 #define RVTEST_MENU_MB_WATERMARK (4000)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	78
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	79 extern void rv_test (UINT32 p);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	80 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	81
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	82
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	83 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	84 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	85 ** Function rvt_init_trace
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	86 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	87 ** Description This function is called by the RV_START task to register
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	88 ** the Riviera Frame in the trace module
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	89 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	90 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	91 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	92 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	93 void rvt_init_trace (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	94 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	95 rvt_register_id ("RV", &rv_trace_user_id, rvt_set_trace_level);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	96 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	97
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	98 #ifdef RVM_ETM_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	99 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	100 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	101 ** Function etm_init_trace
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	102 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	103 ** Description This function is called by the RV_START task to register
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	104 ** the ETM in the trace module
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	105 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	106 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	107 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	108 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	109 void etm_init_trace (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	110 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	111 extern T_RVT_USER_ID tm_trace_user_id;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	112
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	113 rvt_register_id("TM", &etm_trace_user_id, etm_receive);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	114
168 60afcd233b04 gsm-fw: first conditionally-built feature: ETM Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	115 #if 0 //(PSP_STANDALONE != 1)
129 7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	116 tm_trace_user_id = etm_trace_user_id; // TML1 use the tm_trace_user_id
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	117 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	118 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	119 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	120
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	121 #ifdef MIXED_TRACE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	122 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	123 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	124 ** Function l23_init_trace
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	125 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	126 ** Description This function is called by the RV_START task to register
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	127 ** the Protocol Stack (Layers 2 & 3) in the trace module
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	128 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	129 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	130 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	131 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	132 void l23_init_trace (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	133 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	134 rvt_register_id ("L23", &l23_trace_user_id, ext_processExtInput);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	135 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	136 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	137
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	138 #ifdef RVM_RNET_BR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	139 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	140 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	141 ** Function rnet_init_trace
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	142 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	143 ** Description This function is called by the RV_START task to register
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	144 ** RNET in the trace module
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	145 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	146 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	147 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	148 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	149 void rnet_init_trace (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	150 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	151 rvt_register_id ("RNET", &rnet_trace_user_id, rnet_receive);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	152 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	153 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	154
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	155
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	156 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	157 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	158 ** Function rv_start_swe_and_check
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	159 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	160 ** Description This internal function is called by the stater task to
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	161 ** start the basic SWEs in the system and to check if
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	162 ** they started successfully or not.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	163 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	164 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	165 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	166 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	167 BOOLEAN rv_start_swe_and_check (T_RVM_USE_ID swe_use_id, T_RVM_NAME swe_name)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	168 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	169 T_RV_RETURN return_path = {0};
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	170 T_RV_HDR *msg_ptr = NULL;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	171 UINT16 rec_evt = 0;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	172 char error_msg[150] = "";
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	173
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	174 /* temporary initialization of addr_id */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	175 return_path.addr_id = START_TASK_ID;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	176 return_path.callback_func = NULL;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	177
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	178 /* attempt to initialize the required SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	179 if (rvm_start_swe (swe_use_id, return_path) != RVM_OK)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	180 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	181 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	182 "create_RVtasks: Unable to start %s (0x%.8x). Error in rvm_start_swe",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	183 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	184 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	185 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	186 strlen((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	187 NULL_PARAM,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	188 RV_TRACE_LEVEL_WARNING, RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	189 return FALSE;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	190 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	191
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	192 /*
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	193 * wait for the SWE to be actually started.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	194 * note that the 'RVM_EVT_TO_APPLI' notification is sent back
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	195 * once xxx_start () is invoked.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	196 */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	197 while (rec_evt = rvf_evt_wait (START_TASK_ID, \
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	198 0xFFFF, \
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	199 0xFFFFFFFFL))
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	200 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	201 if (rec_evt & ~RVF_TASK_MBOX_0_EVT_MASK)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	202 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	203 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	204 "create_RVtasks: Starting %s (0x%.8x). Event ",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	205 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	206 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	207 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	208 strlen((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	209 (UINT32)rec_evt,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	210 RV_TRACE_LEVEL_WARNING,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	211 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	212 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	213 if (rec_evt & RVF_TASK_MBOX_0_EVT_MASK)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	214 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	215 if ((msg_ptr = (T_RV_HDR *) rvf_read_addr_mbox (START_TASK_ID, \
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	216 RVF_TASK_MBOX_0)) == NULL)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	217 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	218 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	219 "create_RVtasks: Starting %s (0x%.8x). Message NULL",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	220 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	221 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	222 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	223 strlen((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	224 NULL_PARAM,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	225 RV_TRACE_LEVEL_WARNING,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	226 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	227 continue;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	228 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	229 if (msg_ptr->msg_id != RVM_EVT_TO_APPLI)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	230 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	231 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	232 "create_RVtasks: Starting %s (0x%.8x). Message ID ",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	233 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	234 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	235 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	236 strlen((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	237 msg_ptr->msg_id,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	238 RV_TRACE_LEVEL_WARNING,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	239 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	240 rvf_free_buf (msg_ptr);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	241 continue;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	242 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	243 break;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	244 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	245 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	246 switch (((T_RVM_APPLI_RESULT *)msg_ptr)->result)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	247 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	248 case RVM_OK:
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	249 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	250 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	251 "create_RVtasks: %s (0x%.8x) started",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	252 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	253 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	254 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	255 strlen ((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	256 NULL_PARAM,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	257 RV_TRACE_LEVEL_DEBUG_HIGH,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	258 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	259 rvf_free_buf (msg_ptr);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	260 return TRUE;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	261 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	262 case RVM_NOT_READY:
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	263 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	264 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	265 "create_RVtasks: %s (0x%.8x) already started",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	266 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	267 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	268 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	269 strlen ((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	270 NULL_PARAM,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	271 RV_TRACE_LEVEL_DEBUG_MEDIUM,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	272 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	273 rvf_free_buf (msg_ptr);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	274 return TRUE;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	275 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	276 default:
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	277 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	278 break;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	279 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	280 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	281 sprintf (error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	282 "create_RVtasks: Unable to start %s (0x%.8x). Error ",
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	283 (char *)swe_name,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	284 swe_use_id);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	285 rvf_send_trace ((char *)error_msg,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	286 strlen ((char *)error_msg),
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	287 ((T_RVM_APPLI_RESULT *)msg_ptr)->result,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	288 RV_TRACE_LEVEL_WARNING,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	289 RVM_USE_ID);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	290 rvf_free_buf (msg_ptr);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	291 return FALSE;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	292 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	293
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	294 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	295 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	296 ** Function rv_start
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	297 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	298 ** Description This function is called by the RV_START task. It starts the
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	299 ** Riviera environment and the TRACE task. This start must be
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	300 ** done after Application_initialize().
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	301 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	302 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	303 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	304 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	305 void rv_start (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	306 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	307 #if (TEST==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	308 T_RVF_MB_ID mb_id = RVF_INVALID_MB_ID;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	309 T_RVF_MB_PARAM mb_requirements = {0};
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	310 volatile UINT16 result = 0;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	311 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	312
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	313 /* initialize the RVM and the RVF at the same time */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	314 rvm_start_environment ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	315 /*
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	316 ** Init trace module
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	317 */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	318 rvt_init_trace ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	319 #ifdef RVM_ETM_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	320 etm_init_trace ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	321 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	322
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	323 #if CONFIG_GSM
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	324 #ifdef MIXED_TRACE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	325 l23_init_trace ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	326 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	327 #endif // if (_GSM==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	328
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	329 #ifdef RVM_RNET_BR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	330 rnet_init_trace ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	331 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	332
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	333 #if (REMU==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	334 #ifdef RVM_LLS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	335 /* initialize LLS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	336 lls_init();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	337 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	338
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	339 #ifdef RVM_RNG_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	340 /* initialize RNG SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	341 rng_init ();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	342 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	343 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	344
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	345 #ifdef RVM_RVT_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	346 /* initialize TRACE SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	347 rv_start_swe_and_check (RVT_USE_ID, "RVT");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	348 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	349
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	350 #ifdef RVM_I2C_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	351 rv_start_swe_and_check (I2C_USE_ID, "I2C");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	352 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	353
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	354 #ifdef RVM_DMA_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	355 rv_start_swe_and_check (DMA_USE_ID, "DMA");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	356 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	357
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	358 #ifdef RVM_DMG_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	359 rv_start_swe_and_check (DMG_USE_ID, "DMG");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	360 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	361
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	362 #ifdef RVM_NAN_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	363 rv_start_swe_and_check (NAN_USE_ID, "NAN");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	364 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	365
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	366 #ifdef RVM_MC_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	367 rv_start_swe_and_check (MC_USE_ID, "MC");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	368 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	369
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	370 #ifdef RVM_FFS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	371 /* initialize FFS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	372 rv_start_swe_and_check (FFS_USE_ID, "FFS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	373 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	374
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	375 #ifdef RVM_SPI_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	376 /* initialize SPI SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	377 rv_start_swe_and_check (SPI_USE_ID, "SPI");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	378 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	379
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	380 #ifdef RVM_PWR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	381 /* initialize PWR SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	382 rv_start_swe_and_check (PWR_USE_ID, "PWR");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	383 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	384
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	385 #ifdef RVM_LCC_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	386 /* initialize LCC(PWR) SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	387 rv_start_swe_and_check (LCC_USE_ID, "LCC");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	388 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	389
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	390 #ifdef RVM_KPD_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	391 /* initialize KPD SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	392 rv_start_swe_and_check (KPD_USE_ID, "KPD");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	393 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	394
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	395 #ifdef RVM_DAR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	396 /* initialize DAR SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	397 rv_start_swe_and_check (DAR_USE_ID, "DAR");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	398 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	399
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	400 #ifdef RVM_R2D_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	401 /* initialize R2D SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	402 rv_start_swe_and_check (R2D_USE_ID, "R2D");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	403 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	404
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	405 #ifdef RVM_LCD_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	406 /* initialize LCD SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	407 rv_start_swe_and_check (LCD_USE_ID, "LCD");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	408 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	409
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	410
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	411 #ifdef RVM_ETM_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	412 /* initialize ETM SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	413 rv_start_swe_and_check (ETM_USE_ID, "ETM");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	414 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	415
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	416 #ifdef RVM_TTY_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	417 /* initialize TTY SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	418 rv_start_swe_and_check (TTY_USE_ID, "TTY");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	419 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	420
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	421
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	422 #ifdef RVM_AUDIO_MAIN_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	423 /* initialize AUDIO SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	424 rv_start_swe_and_check (AUDIO_USE_ID, "AUDIO");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	425 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	426
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	427 #if 1 //(PSP_STANDALONE==0)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	428 #ifdef RVM_AUDIO_BGD_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	429 /* initialize AUDIO BACKGROUND SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	430 rv_start_swe_and_check (AUDIO_BGD_USE_ID, "AUDIO_BGD");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	431 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	432 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	433
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	434 #if 1 //(PSP_STANDALONE==0)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	435 #ifdef RVM_BAE_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	436 /* initialize BAE SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	437 rv_start_swe_and_check (BAE_USE_ID, "BAE");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	438 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	439 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	440
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	441 #ifdef RVM_AS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	442 /* initialize AS (Audio Services) SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	443 rv_start_swe_and_check (AS_USE_ID, "AS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	444 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	445
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	446 #if 1 //(PSP_STANDALONE==0)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	447 #ifdef RVM_BPR_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	448 /* initialize sample BPR SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	449 rv_start_swe_and_check (BPR_USE_ID, "BPR");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	450 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	451 #endif /* PSP_STANDALONE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	452
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	453 #ifdef RVM_RTC_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	454 /* initialize RTC SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	455 rv_start_swe_and_check (RTC_USE_ID, "RTC");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	456 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	457
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	458 #ifdef RVM_LLS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	459 /* initialize LLS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	460 rv_start_swe_and_check (LLS_USE_ID, "LLS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	461 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	462
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	463 #ifdef RVM_TUT_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	464 /* initialize TUT SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	465 // rv_start_swe_and_check (TUT_USE_ID, "TUT");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	466 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	467
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	468 #ifdef RVM_RGUI_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	469 /* initialize RGUI SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	470 rv_start_swe_and_check (RGUI_USE_ID, "RGUI");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	471 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	472
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	473 #ifdef RVM_ATP_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	474 /* initialize ATP SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	475 rv_start_swe_and_check (ATP_USE_ID, "ATP");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	476 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	477
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	478 #ifdef RVM_MKS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	479 rv_start_swe_and_check (MKS_USE_ID, "MKS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	480 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	481
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	482 #ifdef RVM_IMG_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	483 rv_start_swe_and_check (IMG_USE_ID, "IMG");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	484 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	485
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	486 #ifdef RVM_GBI_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	487 rv_start_swe_and_check (GBI_USE_ID, "GBI");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	488 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	489
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	490 #ifdef RVM_CAMD_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	491 rv_start_swe_and_check (CAMD_USE_ID, "CAMD");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	492 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	493
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	494 #ifdef RVM_USB_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	495 /* initialize USB SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	496 rv_start_swe_and_check (USB_USE_ID, "USB");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	497 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	498
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	499 #ifdef RVM_CAMA_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	500 rv_start_swe_and_check (CAMA_USE_ID, "CAMA");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	501 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	502
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	503 #ifdef RVM_MFW_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	504 /* initialize MFW SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	505 rv_start_swe_and_check (MFW_USE_ID, "MFW");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	506 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	507
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	508 #ifdef RVM_SMBS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	509 /* initialize SMBS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	510 rv_start_swe_and_check (SMBS_USE_ID, "SMBS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	511 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	512
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	513 #ifdef RVM_USBFAX_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	514 /* initialize USB SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	515 rv_start_swe_and_check (USBFAX_USE_ID, "USBFAX");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	516 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	517
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	518 #ifdef RVM_USBTRC_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	519 /* initialize USBTRC SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	520 rv_start_swe_and_check (USBTRC_USE_ID, "USBTRC");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	521 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	522
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	523 #ifdef RVM_USBMS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	524 /* initialize USBMS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	525 rv_start_swe_and_check (USBMS_USE_ID, "USBMS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	526 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	527
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	528 #ifdef RVM_RFS_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	529 /* initialize RFS SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	530 rv_start_swe_and_check (RFS_USE_ID, "RFS");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	531 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	532
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	533
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	534 #ifdef RVM_CCI_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	535 /* initialize CCI SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	536 rv_start_swe_and_check (CCI_USE_ID, "CCI");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	537 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	538
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	539 #ifdef RVM_BTUI_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	540 /* initialize sample BTUI SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	541 rv_start_swe_and_check (BTUI_USE_ID, "BTUI");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	542 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	543 #ifdef RVM_JPEG_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	544 /* initialize sample JPEG SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	545 rv_start_swe_and_check (JPEG_USE_ID, "JPEG");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	546 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	547 #ifdef RVM_JPEG_SWE
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	548 /* initialize sample JPEG SWE */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	549 rv_start_swe_and_check (JPEG_USE_ID, "JPEG");
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	550 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	551 // WARNING WARNING ----------------------------------------------------
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	552 // Do not perform any SWE initialization after this line !
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	553 // WARNING WARNING ----------------------------------------------------
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	554
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	555 #if 0 //(REMU==0)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	556 /* moved this to kpd start function. rv_start function for REMU. rv_start is called from Application Initialize
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	557 context. Since this is a blocking call, we cannot afford to block in Application_Initialization. */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	558 #ifndef _WINDOWS
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	559 // Perform switch ON processing.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	560 Switch_ON();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	561 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	562
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	563 #if (_GSM==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	564 BZ_KeyBeep_ON (); // Audio feedback if ON/OFF pushed
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	565 #endif // if (_GSM==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	566
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	567 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	568
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	569 #if 1 //(CHIPSET!=15) \|\| (REMU==0)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	570 /* dump the Riviera memory state */
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	571 rvf_delay (RVF_MS_TO_TICKS (300)) ;
136 3b5c3f3646fb RV bring-up: lack of timer ticks fixed, Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 129 diff changeset	572 rvf_dump_mem ();
129 7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	573 rvf_dump_pool();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	574 rvf_dump_tasks();
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	575 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	576
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	577 #if (TEST==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	578 // create a Memory Bank for the 'Test Selection Menu'.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	579 mb_requirements.size = RVTEST_MENU_MB_SIZE;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	580 mb_requirements.watermark = RVTEST_MENU_MB_WATERMARK;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	581 mb_requirements.pool_id = RVF_POOL_EXTERNAL_MEM;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	582 if (rvf_create_mb (RVTEST_MENU_MB_NAME,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	583 mb_requirements,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	584 &mb_id) != RVF_OK)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	585 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	586 // error case.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	587 result++;
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	588 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	589
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	590 // Go to the 'Test Selection Menu' (using rv_test ()).
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	591 rv_test (0);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	592 #endif // (TEST==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	593
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	594 // infinite wait
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	595 rvf_evt_wait (START_TASK_ID,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	596 0xFFFF,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	597 0xFFFFFFFFL);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	598 }
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	599
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	600 #if (TEST==1)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	601 #define RV_START_TASK_STACK (4096)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	602 #else
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	603 #define RV_START_TASK_STACK (1024)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	604 #endif
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	605 UINT8 stack_start[RV_START_TASK_STACK];
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	606
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	607
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	608 /*******************************************************************************
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	609 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	610 ** Function create_tasks
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	611 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	612 ** Description This function is called once at startup to allow task
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	613 ** creation thanks to Riviera environment.
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	614 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	615 ** Returns void
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	616 **
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	617 *******************************************************************************/
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	618 void create_tasks (void)
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	619 {
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	620
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	621 // Tasks creation
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	622 rvf_create_legacy_task ((TASKPTR) rv_start, START_TASK_ID,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	623 "RV_START", stack_start,
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	624 RV_START_TASK_STACK, RV_START_TASK_PRIO, 0, RUNNING);
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	625
7d7950d7f924 Riviera should be ready for the first TI fw build attempt Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	626 }

FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/riviera/init/create_RVtasks.c @ 884:353daaa6014d