FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/abb+spi/Makefile @ 665:39bacc7d5c49
gsm-fw: starting to compile comlib
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 28 Sep 2014 05:42:46 +0000 |
parents | 6fd70825db76 |
children |
rev | line source |
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154 | 1 CC= arm-elf-gcc |
2 CFLAGS= -O2 -fno-builtin -mthumb-interwork -mthumb | |
3 LD= arm-elf-ld | |
4 | |
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gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
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parents:
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5 sinclude ../../include/config.mk |
05342cadbaf1
gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
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parents:
157
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6 |
157
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gsm-fw: SPI task code compiles and links
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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7 OBJS= abb.o spi_api.o spi_drv.o spi_env.o spi_process.o spi_task.o |
154 | 8 |
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gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
157
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9 ifeq (${CONFIG_INCLUDE_L1},1) |
591
6fd70825db76
gsm-fw/bsp/abb+spi: abb_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
590
diff
changeset
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10 OBJS+= abb_core_inth.o abb_inth.o |
590
05342cadbaf1
gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
157
diff
changeset
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11 endif |
05342cadbaf1
gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
157
diff
changeset
|
12 |
154 | 13 HDRS= abb.h abb_core_inth.h abb_inline.h abb_inth.h spi_api.h spi_drv.h \ |
14 spi_env.h spi_pool_size.h spi_process.h spi_task.h | |
15 | |
16 all: xipcode.o | |
17 | |
18 ${OBJS}: ${HDRS} | |
19 | |
20 xipcode.o: ${OBJS} | |
21 ${LD} -r -o $@ ${OBJS} | |
22 | |
23 clean: | |
24 rm -f *.[oa] *errs |