FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/cust0/l1_rf12.h @ 368:43ca9d5e30cb
os_evt.c: os_EventGroupInformation(): more bogosity
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Thu, 29 May 2014 05:26:42 +0000 |
parents | 26472940e5b0 |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * |
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4 * Filename l1_rf12.h |
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5 * Copyright 2003 (C) Texas Instruments |
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6 * |
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7 ************* Revision Controle System Header *************/ |
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8 |
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9 #ifndef __L1_RF_H__ |
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10 #define __L1_RF_H__ |
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11 |
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12 #define RF_RITA_10 0x2030 // Check with TIDK |
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13 |
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14 //#define RF_HW_BAND_EGSM |
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15 //#define RF_HW_BAND_DCS |
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16 #define RF_HW_BAND_PCS 0x4 |
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17 #define RF_HW_BAND_DUAL_US 0x80 |
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18 #define RF_HW_BAND_DUAL_EXT 0x20 |
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19 |
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20 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS |
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21 // radio_band_support E-GSM/DCS + GSM850/PCS |
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22 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US) |
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23 |
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24 // L1 RF SW Multiband configuration |
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25 //-------------------------- |
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26 |
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27 // RF_SW_MULTIBAND_SUPPORT values |
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28 #define SINGLE_BAND_900 1 |
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29 #define SINGLE_BAND_1800 2 |
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30 #define SINGLE_BAND_850 3 |
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31 #define SINGLE_BAND_1900 4 |
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32 #define DUAL_BAND_900_1800 5 |
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33 #define DUAL_BAND_850_1900 6 |
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34 #define TRI_BAND_900_1800_1900 7 |
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35 #define TRI_BAND_850_1900_1800 8 |
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36 #define QUAD_BAND 9 |
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37 |
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38 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software |
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39 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1 |
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40 // And also match the RF HW support: RF_HW_BAND_SUPPORT |
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41 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND |
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42 |
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43 // Generate band dependancy options |
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44 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \ |
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45 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) ) |
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46 |
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47 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \ |
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48 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \ |
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49 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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50 |
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51 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \ |
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52 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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53 |
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54 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \ |
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55 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \ |
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56 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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57 |
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58 /************************************/ |
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59 /* SYNTHESIZER setup time... */ |
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60 /************************************/ |
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61 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit. |
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62 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit. |
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63 |
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64 /************************************/ |
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65 /* time for TPU scenario ending... */ |
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66 /************************************/ |
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67 // |
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68 // The following values are used to take into account any TPU activity AFTER |
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69 // BDLON (or BDLENA) down (for RX) and BULON down (for TX) |
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70 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down, |
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71 // these defines must be ZERO |
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72 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down, |
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73 // these defines must be equal to the time difference (in qbits) between |
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74 // the BDLON (or BDLENA) or BULON time and the last TPU command on |
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75 // the TPU scenario |
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76 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down |
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77 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down |
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78 |
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79 |
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80 /******************************************************/ |
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81 /* TXPWR configuration... */ |
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82 /* Fixed TXPWR value when GSM management is disabled. */ |
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83 /******************************************************/ |
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84 |
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85 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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86 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252 |
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87 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE) |
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88 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15 |
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89 #endif |
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90 |
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91 |
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92 /************************************/ |
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93 /* ANALOG delay (in qbits) */ |
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94 /************************************/ |
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95 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal |
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96 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block |
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97 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block |
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98 #if (ANALOG == 1) |
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99 #define UL_ABB_DELAY 3 // modulator input to output delay |
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100 #endif |
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101 #if ((ANALOG == 2) || (ANALOG == 3)) |
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102 #define UL_ABB_DELAY 3 // modulator input to output delay |
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103 #endif |
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104 |
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105 /************************************/ |
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106 /* TX Propagation delay... */ |
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107 /************************************/ |
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108 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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109 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 |
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110 #endif |
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111 |
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112 /************************************/ |
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113 /* Initial value for APC DELAY */ |
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114 /************************************/ |
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115 #if (ANALOG == 1) |
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116 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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117 #define APCDEL_DOWN 2 // minimum value: 2 |
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118 #define APCDEL_UP (6+5) // minimum value: 6 |
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119 #endif |
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120 |
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121 #if (ANALOG == 2) || (ANALOG == 3) |
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122 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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123 #define APCDEL_DOWN (2+0) // minimum value: 2 |
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124 #define APCDEL_UP (6+3+1) // minimum value: 6 |
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125 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8) |
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126 #endif |
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127 |
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128 #define GUARD_BITS 7 |
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129 |
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130 /************************************/ |
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131 /* Initial value for AFC... */ |
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132 /************************************/ |
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133 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced) |
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134 |
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135 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames |
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136 // Rita (RF=12) LDO wakeup requires 6 frames |
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137 |
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138 /************************************/ |
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139 /* Baseband registers */ |
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140 /************************************/ |
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141 #if (ANALOG == 1) |
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142 // Omega registers values will be programmed at 1st DSP communication interrupt |
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143 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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145 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute |
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146 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB |
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147 // RITA does not need an APCOFFSET because the PACTRL is internal: |
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148 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12 |
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149 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) |
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150 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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151 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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152 #define C_DAI_ON_OFF (0x000) // value at reset |
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153 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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154 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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155 // BULRUDEL will be initialized on rach only .... |
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156 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) |
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157 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' |
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158 #endif |
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159 |
152
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160 #if (ANALOG == 2) |
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161 |
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162 // IOTA registers values will be programmed at 1st DSP communication interrupt |
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163 |
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164 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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165 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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166 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB |
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167 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB |
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168 // RITA does not need an APCOFFSET because the PACTRL is internal: |
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169 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128 |
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170 #if (RF_PA == 0 || RF_PA == 3) |
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171 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128 |
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172 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4) |
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173 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128 |
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174 #endif |
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175 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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176 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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177 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset |
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178 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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179 |
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180 |
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181 // audio patch for H2-sample: |
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182 #if (RAZ_VULSWITCH_REGAUDIO == 1) |
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183 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change |
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184 #else |
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185 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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186 #endif |
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187 |
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188 |
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189 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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190 // BULRUDEL will be initialized on rach only .... |
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191 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) |
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192 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) // |
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193 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V |
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194 // Monoslot, Vpp=8/15*Vref |
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195 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB |
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196 #endif |
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197 |
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198 #if (ANALOG == 3) |
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199 |
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200 // SYREN registers values will be programmed at 1st DSP communication interrupt |
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201 |
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202 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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203 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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204 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB |
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205 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB |
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206 #if (RF_PA == 0 || RF_PA == 3) |
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207 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128 |
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208 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4) |
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209 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128 |
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210 #endif |
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211 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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212 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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213 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset |
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214 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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215 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB |
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216 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB |
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217 |
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218 // BULRUDEL will be initialized on rach only .... |
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219 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1) |
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220 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) // |
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221 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V |
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222 // Monoslot, Vpp=8/15*Vref |
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223 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB |
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224 |
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225 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only |
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226 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames |
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227 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero |
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228 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs |
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229 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero |
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230 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero |
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231 |
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232 // SYREN registers values programmed by L1 directly through SPI (ABB_on) |
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233 |
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234 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF |
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235 |
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236 #endif |
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237 |
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238 |
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239 /************************************/ |
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240 /* Automatic frequency compensation */ |
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241 /************************************/ |
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242 /********************* C_Psi_sta definition *****************************/ |
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243 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */ |
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244 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */ |
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245 /* regarding Vega V/N = 2.4/4096 */ |
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246 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */ |
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247 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */ |
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248 /* = 0.000195748 */ |
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249 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */ |
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250 /************************************************************************/ |
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251 |
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252 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta) |
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253 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16 |
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254 #define C_Psi_st_32 634112L // F0.32 |
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255 #define C_Psi_st_inv 6773L // (1/C_Psi_st) |
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256 |
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257 #if (VCXO_ALGO == 1) |
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258 // Linearity parameters |
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259 #define C_AFC_DAC_CENTER ((111)*8) |
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260 #define C_AFC_DAC_MIN ((-1196)*8) |
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261 #define C_AFC_DAC_MAX ((1419)*8) |
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262 |
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263 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10 |
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264 #endif |
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265 |
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266 typedef struct |
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267 { |
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268 WORD16 eeprom_afc; |
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269 UWORD32 psi_sta_inv; |
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270 UWORD32 psi_st; |
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271 UWORD32 psi_st_32; |
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272 UWORD32 psi_st_inv; |
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273 |
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274 #if (VCXO_ALGO) |
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275 // VCXO adjustment parameters |
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276 // Parameters used when assuming linearity |
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277 WORD16 dac_center; |
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278 WORD16 dac_min; |
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279 WORD16 dac_max; |
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280 WORD16 snr_thr; |
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281 #endif |
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282 } |
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283 T_AFC_PARAMS; |
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284 |
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285 /************************************/ |
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286 /* Swap IQ definitions... */ |
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287 /************************************/ |
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288 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */ |
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289 #if (RF_PG == R_PG_10) |
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290 // PG 1.0 -> 1 (Swap RX only) |
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291 // GSM 850 => TX is ALWAYS swapped compared to GSM 900 |
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292 #define SWAP_IQ_GSM 1 |
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293 #define SWAP_IQ_DCS 1 |
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294 #define SWAP_IQ_PCS 1 |
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295 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900 |
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296 #else |
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297 // All PG versions ABOVE 1.0 -> 0 (No Swap) |
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298 // GSM 850 => TX is ALWAYS swapped compared to GSM 900 |
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299 #define SWAP_IQ_GSM 0 |
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300 #define SWAP_IQ_DCS 0 |
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301 #define SWAP_IQ_PCS 0 |
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302 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900 |
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303 #endif |
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304 |
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305 /************************************/ |
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306 /************************************/ |
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307 // typedef |
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308 /************************************/ |
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309 /************************************/ |
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310 |
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311 /*************************************************************/ |
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312 /* Define structure for apc of TX Power ******/ |
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313 /*************************************************************/ |
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314 typedef struct |
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315 { // pcm-file "rf/tx/level.gsm|dcs" |
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316 UWORD16 apc; // 0..31 |
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317 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE |
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318 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE |
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319 } |
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320 T_TX_LEVEL; |
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321 |
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322 /************************************/ |
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323 /* Automatic Gain Control */ |
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324 /************************************/ |
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325 /* Define structure for sub-band definition of TX Power ******/ |
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326 typedef struct |
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327 { |
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328 UWORD16 upper_bound; //highest physical arfcn of the sub-band |
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329 WORD16 agc_calib; // AGC for each TXPWR |
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330 }T_RF_AGC_BAND; |
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331 |
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332 /************************************/ |
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333 /* Ramp definitions */ |
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334 /************************************/ |
152
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335 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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336 typedef struct |
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337 { |
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338 UWORD8 ramp_up [16]; // Ramp-up profile |
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339 UWORD8 ramp_down [16]; // Ramp-down profile |
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340 } |
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341 T_TX_RAMP; |
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342 #endif |
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343 |
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344 |
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345 // RF structure definition |
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346 //======================== |
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347 |
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348 // Number of bands supported |
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349 #define GSM_BANDS 2 |
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350 |
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351 #define MULTI_BAND1 0 |
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352 #define MULTI_BAND2 1 |
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353 // RF table sizes |
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354 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands |
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355 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges |
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356 |
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357 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size |
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358 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table |
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359 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size |
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360 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions |
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361 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges |
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362 |
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363 #define AGC_TABLE_SIZE 20 |
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364 #define MIN_AGC_INDEX 6 |
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365 |
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366 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table |
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367 |
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368 |
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369 // RX parameters and tables |
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370 //------------------------- |
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371 |
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372 // AGC parameters and tables |
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373 typedef struct |
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374 { |
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375 UWORD16 low_agc_noise_thr; |
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376 UWORD16 high_agc_sat_thr; |
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377 UWORD16 low_agc; |
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378 UWORD16 high_agc; |
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379 UWORD8 il2agc_pwr[121]; |
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380 UWORD8 il2agc_max[121]; |
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381 UWORD8 il2agc_av[121]; |
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382 } |
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383 T_AGC; |
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384 |
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385 // Calibration parameters |
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386 typedef struct |
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387 { |
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388 UWORD16 g_magic; |
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389 UWORD16 lna_att; |
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390 UWORD16 lna_switch_thr_low; |
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391 UWORD16 lna_switch_thr_high; |
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392 } |
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393 T_RX_CAL_PARAMS; |
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394 |
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395 // RX temperature compensation |
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396 typedef struct |
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397 { |
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398 WORD16 temperature; |
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399 WORD16 agc_calib; |
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400 } |
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401 T_RX_TEMP_COMP; |
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402 |
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403 // RF RX structure |
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404 typedef struct |
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405 { |
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406 T_AGC agc; |
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407 } |
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408 T_RF_RX; //common |
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409 |
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410 // RF RX structure |
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411 typedef struct |
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412 { |
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413 T_RX_CAL_PARAMS rx_cal_params; |
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414 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE]; |
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415 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE]; |
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416 } |
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417 T_RF_RX_BAND; |
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418 |
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419 |
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420 // TX parameters and tables |
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421 //------------------------- |
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422 |
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423 // TX temperature compensation |
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424 typedef struct |
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425 { |
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426 WORD16 temperature; |
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427 #if (ORDER2_TX_TEMP_CAL==1) |
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428 WORD16 a; |
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429 WORD16 b; |
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430 WORD16 c; |
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431 #else |
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432 WORD16 apc_calib; |
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433 #endif |
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434 } |
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435 T_TX_TEMP_CAL; |
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436 |
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437 // Ramp up and ramp down delay |
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438 typedef struct |
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439 { |
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440 UWORD16 up; |
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441 UWORD16 down; |
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442 } |
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443 T_RAMP_DELAY; |
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444 |
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445 typedef struct |
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446 { |
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447 UWORD16 arfcn_limit; |
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448 WORD16 chan_cal; |
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449 } |
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450 T_TX_CHAN_CAL; |
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451 |
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452 // RF TX structure |
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453 typedef struct |
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454 { |
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455 T_RAMP_DELAY ramp_delay; |
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456 UWORD8 guard_bits; // number of guard bits needed for ramp up |
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457 UWORD8 prg_tx; |
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458 } |
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459 T_RF_TX; //common |
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460 |
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461 // RF TX structure |
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462 typedef struct |
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463 { |
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464 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE]; |
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465 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS]; |
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466 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE]; |
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467 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE]; |
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468 } |
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469 T_RF_TX_BAND; |
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470 |
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471 // band structure |
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472 typedef struct |
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473 { |
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474 T_RF_RX_BAND rx; |
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475 T_RF_TX_BAND tx; |
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476 UWORD8 swap_iq; |
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477 } |
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478 T_RF_BAND; |
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479 |
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480 // RF structure |
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481 typedef struct |
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482 { |
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483 // common for all bands |
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484 UWORD16 rf_revision; |
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485 UWORD16 radio_band_support; |
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486 T_RF_RX rx; |
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487 T_RF_TX tx; |
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488 T_AFC_PARAMS afc; |
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489 } |
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490 T_RF; |
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491 |
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492 /************************************/ |
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493 /* MADC definitions */ |
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494 /************************************/ |
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495 // Omega: 5 external channels if touch screen not used, 3 otherwise |
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496 enum ADC_INDEX { |
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497 ADC_VBAT, |
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498 ADC_VCHARG, |
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499 ADC_ICHARG, |
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500 ADC_VBACKUP, |
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501 ADC_BATTYP, |
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502 ADC_BATTEMP, |
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503 ADC_ADC3, // name of this ?? |
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504 ADC_RFTEMP, |
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505 ADC_ADC4, |
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506 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums |
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507 }; |
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508 |
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509 typedef struct |
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510 { |
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511 WORD16 converted[ADC_INDEX_END]; // converted |
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512 UWORD16 raw[ADC_INDEX_END]; // raw from ADC |
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513 } |
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514 T_ADC; |
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515 |
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516 /************************************/ |
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517 /* MADC calibration */ |
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518 /************************************/ |
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519 typedef struct |
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520 { |
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521 UWORD16 a[ADC_INDEX_END]; |
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522 WORD16 b[ADC_INDEX_END]; |
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523 } |
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524 T_ADCCAL; |
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525 |
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526 // Conversion table: ADC value -> temperature |
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527 typedef struct |
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528 { |
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529 UWORD16 adc; // ADC reading is 10 bits |
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530 WORD16 temp; // temp is in approx. range -30..+80 |
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531 } |
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532 T_TEMP; |
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533 |
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534 typedef struct |
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535 { |
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536 char *name; |
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537 void *addr; |
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538 int size; |
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539 } |
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540 T_CONFIG_FILE; |
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541 |
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542 typedef struct |
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543 { |
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544 char *name; // name of ffs file suffix |
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545 T_RF_BAND *addr; // address to default flash structure |
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546 UWORD16 max_carrier; // max carrier |
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547 UWORD16 max_txpwr; // max tx power |
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548 } |
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549 T_BAND_CONFIG; |
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550 |
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551 typedef struct |
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552 { |
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553 UWORD8 band[GSM_BANDS]; // index to band address |
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554 UWORD8 txpwr_tp; // tx power turning point |
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555 UWORD16 first_arfcn; // first index |
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556 } |
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557 T_STD_CONFIG; |
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558 enum GSMBAND_DEF |
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559 { |
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560 BAND_NONE, |
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561 BAND_EGSM900, |
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562 BAND_DCS1800, |
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563 BAND_PCS1900, |
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564 BAND_GSM850, |
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565 // put new bands here |
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566 BAND_GSM900 //last entry |
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567 }; |
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568 |
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569 /************************************/ |
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570 /* ABB (Omega) Initialization */ |
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571 /************************************/ |
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572 |
152
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573 #if ((ANALOG == 1) || (ANALOG == 2)) |
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574 #define ABB_TABLE_SIZE 16 |
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575 #elif (ANALOG == 3) |
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576 #define ABB_TABLE_SIZE 22 |
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577 #endif |
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578 |
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579 // Note that this translation is probably not needed at all. But until L1 is |
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580 // (maybe) changed to simply initialize the ABB from a table of words, we |
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581 // use this to make things more easy-readable. |
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582 |
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583 #if (ANALOG == 1) |
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584 enum ABB_REGISTERS { |
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585 ABB_AFCCTLADD = 0, |
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586 ABB_VBUCTRL, |
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587 ABB_VBDCTRL, |
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588 ABB_BBCTRL, |
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589 ABB_APCOFF, |
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590 ABB_BULIOFF, |
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591 ABB_BULQOFF, |
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592 ABB_DAI_ON_OFF, |
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parents:
diff
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593 ABB_AUXDAC, |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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594 ABB_VBCTRL, |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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595 ABB_APCDEL1 |
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parents:
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596 }; |
152
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parents:
151
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597 #elif (ANALOG == 2) |
151
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598 enum ABB_REGISTERS { |
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599 ABB_AFCCTLADD = 0, |
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parents:
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600 ABB_VBUCTRL, |
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parents:
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601 ABB_VBDCTRL, |
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parents:
diff
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602 ABB_BBCTRL, |
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parents:
diff
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603 ABB_BULGCAL, |
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parents:
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604 ABB_APCOFF, |
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parents:
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605 ABB_BULIOFF, |
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parents:
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606 ABB_BULQOFF, |
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parents:
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607 ABB_DAI_ON_OFF, |
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parents:
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608 ABB_AUXDAC, |
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parents:
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changeset
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609 ABB_VBCTRL1, |
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parents:
diff
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610 ABB_VBCTRL2, |
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parents:
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611 ABB_APCDEL1, |
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parents:
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612 ABB_APCDEL2 |
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parents:
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613 }; |
152
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parents:
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614 #elif (ANALOG == 3) |
151
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615 enum ABB_REGISTERS { |
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parents:
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616 ABB_AFCCTLADD = 0, |
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parents:
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617 ABB_VBUCTRL, |
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parents:
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618 ABB_VBDCTRL, |
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parents:
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619 ABB_BBCTRL, |
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parents:
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620 ABB_BULGCAL, |
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parents:
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621 ABB_APCOFF, |
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parents:
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622 ABB_BULIOFF, |
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parents:
diff
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623 ABB_BULQOFF, |
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parents:
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624 ABB_DAI_ON_OFF, |
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parents:
diff
changeset
|
625 ABB_AUXDAC, |
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parents:
diff
changeset
|
626 ABB_VBCTRL1, |
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parents:
diff
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|
627 ABB_VBCTRL2, |
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parents:
diff
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|
628 ABB_APCDEL1, |
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parents:
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|
629 ABB_APCDEL2, |
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parents:
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630 ABB_VBPOP, |
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parents:
diff
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|
631 ABB_VAUDINITD, |
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parents:
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|
632 ABB_VAUDCTRL, |
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parents:
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|
633 ABB_VAUOCTRL, |
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parents:
diff
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|
634 ABB_VAUSCTRL, |
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parents:
diff
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|
635 ABB_VAUDPLL |
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parents:
diff
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|
636 }; |
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parents:
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|
637 #endif |
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|
638 #endif |