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nuc-fw: beginning to integrate TI's BSP code
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 31 Aug 2013 23:43:23 +0000
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children 91460c8957f0
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : clkm.h
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12
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13 Description : Header file for the CLKM module
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14
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15 Project : drivers
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16
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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18
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19 Version number : 1.10
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20
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21 Date and time : 10/23/01 14:34:54
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22
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23 Previous delta : 10/19/01 15:25:25
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24
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
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26
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27 Sccs Id (SID) : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
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28
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29
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30 *****************************************************************************/
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31
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32 #include "../include/config.h"
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33 #include "../include/sys_types.h"
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34
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35 #define CLKM_ARM_CLK MEM_CLKM_ADDR /* CLKM ARM CLock Control reg.*/
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36 #define CLKM_MCLK_EN 0x0001
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37
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38
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39 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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40 #define MASK_CLKIN 0x0006
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41 #endif
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42
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43 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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44 #define CLKM_CLKIN0 0x0002 // Mask to select between DPLL and VTCXO or CLKIN
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45 #else
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46 #define CLKM_LOW_FRQ 0x0002 // Mask to select low frequency input CLK_32K
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47 #endif
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48 #define CLKM_CLKIN_SEL 0x0004 // Mask to select between VTCXO and CLKIN
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49
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50 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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51 #define CLKM_ARM_MCLK_XP5 0x0008 // Mask to enable the 1.5 or 2.5 division factor
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52 #define CLKM_MCLK_DIV 0x0070 // Mask to configure the division factor
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53 #else
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54 #define MASK_ARM_MCLK_1P5 0x0008 // Mask to enable the 1.5 division factor
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55 #define CLKM_MCLK_DIV 0x0030 // Mask to configure the division factor
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56 #endif
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57
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58 #define CLKM_DEEP_PWR 0x0f00 // Mask to configure deep power
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59 #define CLKM_DEEP_SLEEP 0x1000 // Mask to configure deep sleep
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60
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61 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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62 #define CLKM_SEL_DPLL 0x0000 // Selection of DPLL for ARM clock generation
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63 #define CLKM_SEL_VTCXO 0x0001 // Selection of VTCXO for ARM clock generation
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64 #define CLKM_SEL_CLKIN 0x0003 // Selection of CLKIN for ARM clock generation
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65
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66 #define CLKM_ENABLE_XP5 0x0001 // Enable 1.5 or 2.5 division factor
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67 #define CLKM_DISABLE_XP5 0x0000 // Disable 1.5 or 2.5 division factor
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68
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69 #define CLKM_ARM_MCLK_DIV_OFFSET 4 // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
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70
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71 #define CLKM_ARM_CLK_RESET 0x1081 // Reset value of CNTL_ARM_CLK register
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72 #endif
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73
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74 #define CLKM_CNTL_ARM_CLK (MEM_CLKM_ADDR + 0x00)
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75 #define CLKM_CNTL_CLK (MEM_CLKM_ADDR + 2) /* CLKM Clock Control reg. */
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76
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77 #define CLKM_IRQ_DIS 0x0001 // IRQ clock is disabled and enabled according to the sleep command
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78 #define CLKM_BRIDGE_DIS 0x0002 // BRIDGE clock is disabled and enabled according to the sleep command
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79 #define CLKM_TIMER_DIS 0x0004 // TIMER clock is disabled and enabled according to the sleep command
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80 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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81 #define CLKM_DPLL_DIS 0x0008 // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
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82 #else
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83 #define CLKM_PLL_SEL 0x0008 // CLKIN input is connected to the PLL
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84 #endif
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85 #define CLKM_CLKOUT_EN 0x0010 // Enable CLKOUT(2:0) output clocks
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86 #if (CHIPSET == 4)
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87 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
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88 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
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89 #elif (CHIPSET == 6)
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90 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
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91 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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92 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
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93 #define CLKM_VCLKOUT_2 0x0040 // VTCXO is divided by 2
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94 #define CLKM_VTCXO_2 0x0080 // Input clock to DPLL is divided by 2
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95 #endif
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96
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97 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
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98 #define CLKM_LEAD_RST 0x0002
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99 #define CLKM_EXT_RST 0x0004
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100
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101 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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102 #define DPLL_LOCK 0x0001 // Mask of DPLL lock status
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103 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
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104 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
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105 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
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106 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
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107
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108 #define DPLL_BYPASS_DIV_1 0x00 // Configuration of bypass mode divided by 1
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109 #define DPLL_BYPASS_DIV_2 0x01 // Configuration of bypass mode divided by 2
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110 #define DPLL_BYPASS_DIV_4 0x10 // Configuration of bypass mode divided by 4
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111
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112 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
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113 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
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114 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
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115
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116 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
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117 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
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118 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
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119 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
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120
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121 #else
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122 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
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123 #define CLKM_PLONOFF 0x0001 // PLL enable signal
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124 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
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125 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
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126 #define CLKM_PLDIV 0x0040 // Mask of multiply factor configuration
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127 #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
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128 #endif
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129
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130 #if (CHIPSET == 12)
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131 #define CLKM_CNTL_CLK_DSP (MEM_CLKM_ADDR + 0x8A) /* CLKM CNTL_CLK_REG register */
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132
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133 #define CLKM_NB_DSP_DIV_VALUE 4
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134
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135 #define CLKM_DSP_DIV_1 0x00
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136 #define CLKM_DSP_DIV_1_5 0x01
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137 #define CLKM_DSP_DIV_2 0x02
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138 #define CLKM_DSP_DIV_3 0x03
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139
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140 #define CLKM_DSP_DIV_MASK 0x0003
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141
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142 extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
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143
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144 /*---------------------------------------------------------------/
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145 /* CLKM_DSP_DIV_FACTOR() */
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146 /*--------------------------------------------------------------*/
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147 /* Parameters : none */
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148 /* Return : none */
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149 /* Functionality : Set the DSP division factor */
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150 /*--------------------------------------------------------------*/
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151
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152 #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
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153
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154
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155 /*---------------------------------------------------------------/
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156 /* CLKM_READ_DSP_DIV() */
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157 /*--------------------------------------------------------------*/
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158 /* Parameters : none */
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159 /* Return : none */
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diff changeset
160 /* Functionality : Read DSP division factor */
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161 /*--------------------------------------------------------------*/
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162
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163 #define CLKM_READ_DSP_DIV ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
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164
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165 #define CLKM_GET_DSP_DIV_VALUE dsp_div_value[CLKM_READ_DSP_DIV]
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166
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167 #endif
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168
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169
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170 /*---------------------------------------------------------------/
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171 /* CLKM_SETLEADRESET() */
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172 /*--------------------------------------------------------------*/
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173 /* Parameters : none */
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174 /* Return : none */
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175 /* Functionality : Set the LEAD reset signal */
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176 /*--------------------------------------------------------------*/
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177
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178 #define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
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179
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180 /*---------------------------------------------------------------/
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181 /* CLKM_RELEASELEADRESET() */
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182 /*--------------------------------------------------------------*/
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183 /* Parameters : none */
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184 /* Return : none */
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185 /* Functionality : Release the LEAD reset signal */
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186 /*--------------------------------------------------------------*/
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187
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188 #define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
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189
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190 /*---------------------------------------------------------------/
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diff changeset
191 /* CLKM_SETEXTRESET() */
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diff changeset
192 /*--------------------------------------------------------------*/
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193 /* Parameters : none */
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194 /* Return : none */
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diff changeset
195 /* Functionality : Set the external reset signal */
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196 /*--------------------------------------------------------------*/
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197
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198 #define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
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199
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diff changeset
200 /*---------------------------------------------------------------/
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diff changeset
201 /* CLKM_CLEAREXTRESET() */
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diff changeset
202 /*--------------------------------------------------------------*/
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diff changeset
203 /* Parameters : none */
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diff changeset
204 /* Return : none */
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parents:
diff changeset
205 /* Functionality : Clear the external reset signal */
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diff changeset
206 /*--------------------------------------------------------------*/
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207
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208 #define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
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209
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diff changeset
210
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diff changeset
211 /*---------------------------------------------------------------/
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diff changeset
212 /* CLKM_POWERDOWNARM() */
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diff changeset
213 /*--------------------------------------------------------------*/
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diff changeset
214 /* Parameters : none */
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215 /* Return : none */
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diff changeset
216 /* Functionality : Power down the ARM mcu */
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diff changeset
217 /*--------------------------------------------------------------*/
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218 #define CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
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219
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diff changeset
220 /*---------------------------------------------------------------/
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diff changeset
221 /* CLKM_SET1P5() */
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diff changeset
222 /*--------------------------------------------------------------*/
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diff changeset
223 /* Parameters : none */
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224 /* Return : none */
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diff changeset
225 /* Functionality : Set ARM_MCLK_1P5 bit */
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226 /*--------------------------------------------------------------*/
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227
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228 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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diff changeset
229 #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
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diff changeset
230 #else
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231 #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
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232 #endif
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diff changeset
233
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diff changeset
234 /*---------------------------------------------------------------/
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diff changeset
235 /* CLKM_RESET1P5() */
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parents:
diff changeset
236 /*--------------------------------------------------------------*/
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diff changeset
237 /* Parameters : none */
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238 /* Return : none */
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diff changeset
239 /* Functionality : Reset ARM_MCLK_1P5 bit */
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diff changeset
240 /*--------------------------------------------------------------*/
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diff changeset
241
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diff changeset
242 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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diff changeset
243 #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
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diff changeset
244 #else
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diff changeset
245 #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
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246 #endif
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diff changeset
247
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248 /*---------------------------------------------------------------/
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diff changeset
249 /* CLKM_INITCNTL() */
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diff changeset
250 /*--------------------------------------------------------------*/
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parents:
diff changeset
251 /* Parameters : value to write in the CNTL register */
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diff changeset
252 /* Return : none */
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253 /* Functionality :Initialize the CLKM Control Clock register */
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254 /*--------------------------------------------------------------*/
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255
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256 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)
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257
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258
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259 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
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260 /*---------------------------------------------------------------/
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261 /* CLKM_INITLEADPLL() */
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262 /*--------------------------------------------------------------*/
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263 /* Parameters : value to write in the CNTL_PLL LEAD register */
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264 /* Return : none */
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265 /* Functionality :Initialize LEAD PLL control register */
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266 /*--------------------------------------------------------------*/
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267
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268 #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
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269 #endif
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270
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271 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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272 /*---------------------------------------------------------------/
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273 /* CLKM_DPLL_SWITH_OFF_MODE_CONFIG() */
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274 /*--------------------------------------------------------------*/
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275 /* Parameters : None */
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276 /* Return : none */
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277 /* Functionality : Configure DPLL switch off mode */
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278 /*--------------------------------------------------------------*/
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279
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280 #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
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281 (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
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282
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283 /*---------------------------------------------------------------/
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284 /* CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG() */
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285 /*--------------------------------------------------------------*/
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286 /* Parameters : None */
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287 /* Return : none */
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288 /* Functionality : Reset configuration of DPLL switch off mode */
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289 /*--------------------------------------------------------------*/
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290
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291 #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
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292 ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
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293
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294 /*---------------------------------------------------------------/
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295 /* CLKM_FORCE_API_HOM_IN_IDLE3() */
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296 /*--------------------------------------------------------------*/
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297 /* Parameters : None */
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298 /* Return : none */
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299 /* Functionality : SAM/HOM wait-state register force to HOM when*/
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300 /* DSP is in IDLE3 mode */
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301 /*--------------------------------------------------------------*/
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302
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303 #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
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304
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305 #if (CHIPSET == 4)
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306 /*---------------------------------------------------------------/
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307 /* CLKM_USE_VTCXO_26MHZ() */
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308 /*--------------------------------------------------------------*/
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309 /* Parameters : None */
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310 /* Return : none */
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311 /* Functionality : Divide by 2 the clock used by the peripheral */
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312 /* when using external VTCXO at 26 MHz instead */
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313 /* of 13MHz */
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314 /*--------------------------------------------------------------*/
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315
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316 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
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317
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318 /*---------------------------------------------------------------/
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319 /* CLKM_UNUSED_VTCXO_26MHZ() */
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320 /*--------------------------------------------------------------*/
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321 /* Parameters : None */
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322 /* Return : none */
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323 /* Functionality : Use VTCXO=13MHz */
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324 /*--------------------------------------------------------------*/
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325
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326 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
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327 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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diff changeset
328 /*---------------------------------------------------------------/
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329 /* CLKM_UNUSED_VTCXO_26MHZ() */
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330 /*--------------------------------------------------------------*/
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331 /* Parameters : None */
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diff changeset
332 /* Return : none */
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333 /* Functionality : Use VTCXO=13MHz */
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334 /*--------------------------------------------------------------*/
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335
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336 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
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337
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338 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
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339 #endif
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340
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341
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342 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
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343 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
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344
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345 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
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346 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
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347 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
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diff changeset
348 }
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349
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350 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
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351 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
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352 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
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353 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
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diff changeset
354 }
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355
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356 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
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357 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
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358 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
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359
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360
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361 #endif
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362
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363 /* ----- Prototypes ----- */
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364
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365 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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366 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
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367 #else
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368 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
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369 #endif
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370
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371 void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
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372 void initialize_wait_loop(void);
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373 inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);