FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/finlink/ld-script.src @ 816:48b1b5e26a1e
g23m-aci/aci/Makefile: link xipcode.o
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Sun, 05 Apr 2015 08:19:16 +0000 |
parents | 210268d8e553 |
children | 2d3f29ef866d |
rev | line source |
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1 dnl This ld script source is fed through m4 in order to fill in |
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2 dnl those settings which depend on the configuration. |
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3 dnl Memory region sizes are set in ../include/config.m4, generated |
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4 dnl by the configuration mechanism based on the selected target, |
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5 dnl and the Makefile prepends flash.m4 or xram.m4 to select the |
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6 dnl type of image we are linking: either the regular flashable image, |
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7 dnl or a RAM-only test image (to be loaded via fc-xram) that does not |
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8 dnl touch the flash and pretends as if the flash doesn't even exist. |
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9 |
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10 /* |
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11 * FreeCalypso ld script for the Buildmem build |
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12 */ |
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13 |
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14 ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,_Flash_boot_entry)) |
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15 |
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16 include(`../include/config.m4')dnl |
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17 MEMORY { |
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18 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1, |
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19 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000') |
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20 ifelse(Buildmem,FLASH, |
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21 ` FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR, |
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22 LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR') |
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23 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE |
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24 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE |
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25 } |
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26 ifelse(FFS_IN_RAM,1,` |
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27 RAMFFS_BLKSIZE_BYTES = 1 << RAMFFS_BLKSIZE_LOG2; |
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28 RAMFFS_TOTAL_SIZE = RAMFFS_BLKSIZE_BYTES * RAMFFS_NBLOCKS; |
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29 ')dnl |
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30 |
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31 SECTIONS { |
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32 dnl The following sections exist only in the flashImage build, |
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33 dnl and only on targets that use the Calypso boot ROM. |
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34 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1, |
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35 ` /* Part of flash overlaid by the boot ROM */ |
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36 bootrom.overlay 0 : { |
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37 *(bootrom.overlay) |
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38 } > FLASH_OVERLAY |
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39 |
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40 /* code that enables the boot ROM and jumps to it */ |
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41 bootrom.switch : { |
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42 *(bootrom.switch) |
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43 } > IRAM AT> FLASH_OVERLAY |
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44 __romswitch_ram_addr = ADDR(bootrom.switch); |
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45 __romswitch_flash_addr = LOADADDR(bootrom.switch); |
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46 __romswitch_size = SIZEOF(bootrom.switch); |
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47 ')dnl |
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48 |
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49 dnl all flashImage builds |
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50 ifelse(Buildmem,FLASH, |
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51 ` /* Flash boot entry point */ |
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52 flashboot.text FLASHIMAGE_BASE_ADDR : { |
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53 *(flashboot.text) |
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54 } > FLASH |
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55 ')dnl |
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56 |
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57 /* XIP code, going into flash or XRAM emulating flash */ |
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58 xip.text : { |
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59 *(xip.text*) |
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60 xipcode.o(.text*) |
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61 *comlib.a:(.text*) |
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62 *libplus.xip.a:(.text*) |
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63 *libgpf.xip.a:(.text*) |
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64 *libccd.a:(.text*) |
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65 *librv.a:(.text*) |
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66 *libsprintf.a:(.text*) |
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67 /* let's put the ARM->Thumb veneers in the XIP section */ |
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68 *(.glue_7) |
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69 } > Buildmem |
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70 |
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71 /* copy-to-IRAM code */ |
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72 iram.text 0x80001C : { |
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73 /* the 7 exception and interrupt vectors @ 0x80001C */ |
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74 *(iram.vectors) |
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75 *(iram.text*) |
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76 iramcode.o(.text*) |
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77 *libplus.iram.a:(.text*) |
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78 *libgpf.iram.a:(.text*) |
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79 *libc.a:(.text*) |
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80 *libgcc.a:(.text*) |
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81 } > IRAM Put_in_flash |
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82 ifelse(Buildmem,FLASH, |
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83 ` __iramtext_ram_addr = ADDR(iram.text); |
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84 __iramtext_flash_addr = LOADADDR(iram.text); |
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85 __iramtext_size = SIZEOF(iram.text); |
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86 ')dnl |
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87 |
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88 /* all .rodata will stay in flash */ |
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89 .rodata : { |
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90 *(.rodata*) |
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91 } > Buildmem |
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92 |
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93 /* |
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94 * All .data will go into XRAM. |
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95 * For the flash build we'll have a step that copies |
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96 * the .data section from flash to XRAM; for the RAM-only |
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97 * build it goes directly into XRAM and stays there. |
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98 */ |
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99 .data : { |
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100 *(.data*) |
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101 } > XRAM Put_in_flash |
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102 ifelse(Buildmem,FLASH, |
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103 ` __initdata_ram_addr = ADDR(.data); |
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104 __initdata_flash_addr = LOADADDR(.data); |
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105 __initdata_size = SIZEOF(.data); |
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106 ')dnl |
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107 |
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108 /* we have two kinds of BSS: internal and external */ |
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109 int.bss (NOLOAD) : { |
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110 *(int.bss*) |
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111 *(.l1s_global) |
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112 iramcode.o(.bss* COMMON) |
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113 *libplus.iram.a:(.bss* COMMON) |
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114 *libgpf.iram.a:(.bss* COMMON) |
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115 *libc.a:(.bss* COMMON) |
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116 *libgcc.a:(.bss* COMMON) |
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117 . = ALIGN(4); |
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118 } > IRAM |
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119 __intbss_start = ADDR(int.bss); |
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120 __intbss_size = SIZEOF(int.bss); |
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121 |
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122 ext.bss (NOLOAD) : { |
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123 *(ext.bss*) |
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124 xipcode.o(.bss* COMMON) |
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125 *comlib.a:(.bss* COMMON) |
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126 *libplus.xip.a:(.bss* COMMON) |
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127 *libgpf.xip.a:(.bss* COMMON) |
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128 *libccd.a:(.bss* COMMON) |
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129 *librv.a:(.bss* COMMON) |
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130 *libsprintf.a:(.bss* COMMON) |
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131 . = ALIGN(4); |
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132 } > XRAM |
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133 __extbss_start = ADDR(ext.bss); |
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134 __extbss_size = SIZEOF(ext.bss); |
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135 |
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136 /* finally, we have "raw RAM": like BSS, but we don't zero it out */ |
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137 int.ram (NOLOAD) : { |
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138 *(int.ram*) |
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139 *(system_stack) |
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140 *(irq_stack) |
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141 *(fiq_stack) |
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142 *(timer_hisr_stack) |
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143 . = ALIGN(4); |
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144 _iram_end = .; |
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145 } > IRAM |
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146 |
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147 ext.ram (NOLOAD) : { |
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148 *(ext.ram*) |
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149 *(except_stack) |
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150 . = ALIGN(4); |
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151 ifelse(FFS_IN_RAM,1, |
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152 ` _RAMFFS_area = .; |
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153 . += RAMFFS_TOTAL_SIZE; |
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154 ')dnl |
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155 _xram_end = .; |
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156 } > XRAM |
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157 } |