freecalypso-sw: gsm-fw/L1/include/l1

annotate gsm-fw/L1/include/l1_confg.h @ 356:4e0aa166baa5

target-utils/tf-breakin: payload written for the TF C139 break-in attempt

author	Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date	Thu, 15 May 2014 09:18:23 +0000
parents	d0de2d0a426d
children	2c9c2b95ddec

rev	line source
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	1 /*********** Revision Controle System Header ***********
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	2 * GSM Layer 1 software
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	3 * L1_CONFG.H
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	4 *
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	5 * Filename l1_confg.h
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	7 *
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	8 *********** Revision Controle System Header ***********/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	9
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	10 #ifndef __L1_CONFG_H__
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	11 #define __L1_CONFG_H__
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	12
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	13 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	16 // TRACE_TYPE == 1 -> L1/L3 interface trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	17 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	18 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	19 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	20 // TRACE_TYPE == 5 -> trace for full simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	21 // TRACE_TYPE == 6 -> CPU load trace for hisr
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	22 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	23 // UART at 38400 bps =>
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	24 // format : <hisr cpu value in microseconds> <frame number>
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	25
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	26 // Code PB reported workaround
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	27 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	28
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	29
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	30 // Code Version possible choices
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	31 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	32 #define SIMULATION 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	33 #define NOT_SIMULATION 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	34
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	35 // RCL functions Version possible choices
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	36 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	37 #define POLL_FORCED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	38 #define RLC_SCENARIO 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	39 #define MODEM_FLOW 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	40
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	41 // possible choices for UART trace output
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	42 //------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	43 #define MODEM_UART 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	44 #define IRDA_UART 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	45 #if (CHIPSET == 12)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	46 #define MODEM2_UART 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	47 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	48
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	49 //============
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	50 // CODE CHOICE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	51 //============
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	52 #if 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	53 #if (OP_L1_STANDALONE==0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	54 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	55 #else // OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	56 #ifdef WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	57 #define CODE_VERSION SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	58 #else // WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	59 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	60 #endif // WIN32
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	61 #endif // OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	62 #endif // #if 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	63
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	64 /* FreeCalypso */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	65 #define CODE_VERSION NOT_SIMULATION
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	66 #define AMR 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	67 #define L1_12NEIGH 1
150 3c850b416c9a integrating more L1 header files needed by the abb+spi code Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	68 #define L1_DYN_DSP_DWNLD 1
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	69 #define L1_EOTD 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	70 #define L1_GTT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	71 #define MELODY_E2 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	72 #define TESTMODE 1
150 3c850b416c9a integrating more L1 header files needed by the abb+spi code Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 143 diff changeset	73 #define TRACE_TYPE 4
151 d0de2d0a426d more L1 header files brought in Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: 150 diff changeset	74 #define VCXO_ALGO 1
115 1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	75
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	76 #if CONFIG_GPRS
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	77 # define L1_GPRS 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	78 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	79 # define L1_GPRS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	80 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	81
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	82 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	83 // Test with full simulation.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	84 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	85 #if (CODE_VERSION == SIMULATION)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	86
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	87 // Test Scenari...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	88 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	89 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	90
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	91 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	92 #undef TRACE_TYPE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	93 #define TRACE_TYPE 5
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	94 #define LOGFILE_TRACE 1 // trace in an output logfile
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	95 #define FLOWCHART 0 // Message sequence/flow chart trace.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	96 #define NUCLEUS_TRACE 0 // Nucleus error trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	97 #define EOTD_TRACE 1 // EOTD log trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	98 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	99
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	100 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	101
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	102 // Control algorithms...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	103 #define AFC_ALGO 1 // AFC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	104 #define TOA_ALGO 1 // TOA algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	105 #define AGC_ALGO 1 // AGC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	106 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	107 #undef VCXO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	108 #define VCXO_ALGO 0 // VCXO algo
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	109 #undef DCO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	110 #define DCO_ALGO 0 // DCO algo (TIDE)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	111 #undef ORDER2_TX_TEMP_CAL
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	112 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	113
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	114
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	115 #define FACCH_TEST 0 // FACCH test enabled.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	116
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	117 #define ADC_TIMER_ON 0 // Timer for ADC measurements
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	118 #define AFC_ON 1 // Enable of the Omega AFC module
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	119
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	120 #define AUDIO_TASK 1 // Enable the L1 audio features
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	121 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	122 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	123
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	124 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	125 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	126 #define TTY_SYNC_MCU_2 1 //
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	127 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	128 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	129 #define OPTIMISED 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	130
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	131 #define L1_RECOVERY 0 // L1 recovery
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	132
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	133 #undef L1_GPRS
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	134 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	135
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	136 #undef AMR
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	137 #define AMR 1 // AMR version 1.0 supported
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	138
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	139 #undef L1_12NEIGH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	140 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	141
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	142 #undef L1_GTT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	143 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	144
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	145 #undef OP_L1_STANDALONE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	146 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	147
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	148 #undef OP_RIV_AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	149 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	150
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	151 #undef OP_WCP
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	152 #define OP_WCP 0 // No WCP integration
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	153 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	154 // Test with H/W platform.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	155 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	156 #elif (CODE_VERSION == NOT_SIMULATION)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	157
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	158 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	159 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	160 // (corrected with Calypso ReV B and Calypso C035)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	161 #if (CHIPSET == 7)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	162 #define W_A_CALYPSO_BUG_01435 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	163 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	164 #define W_A_CALYPSO_BUG_01435 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	165 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	166
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	167
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	168 // for AMR thresolds definition CQ22226
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	169 #define AMR_THRESHOLDS_WORKAROUND 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	170
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	171 #if (L1_GTT==1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	172 #define TTY_SYNC_MCU 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	173 #define TTY_SYNC_MCU_2 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	174 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	175 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	176 #define OPTIMISED 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	177 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	178 #define TTY_SYNC_MCU_2 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	179 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	180 #define TTY_SYNC_MCU 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	181 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	182 #define OPTIMISED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	183
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	184 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	185
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	186 // Traces...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	187 #define NUCLEUS_TRACE 0 // Nucleus error trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	188 #define FLOWCHART 0 // Message sequence/flow chart trace.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	189 #define LOGFILE_TRACE 0 // trace in an output logfile
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	190 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	191
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	192 // Test Scenari...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	193 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	194 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	195
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	196 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	197 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	198 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	199 #define L2_L3_SIMUL 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	200 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	201
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	202 // Control algorithms...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	203 #define AFC_ALGO 1 // AFC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	204 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	205 #define TOA_ALGO 1 // TOA algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	206 #define AGC_ALGO 1 // AGC algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	207 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	208
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	209 #define FACCH_TEST 0 // FACCH test enabled.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	210
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	211 #define ADC_TIMER_ON 0 // Timer for ADC measurements
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	212 #define AFC_ON 1 // Enable of the Omega AFC module
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	213
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	214 #define AUDIO_TASK 1 // Enable the L1 audio features
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	215 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	216 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	217 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	218 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	219 #define AUDIO_L1_STANDALONE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	220 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	221
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	222 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	223
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	224 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	225
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	226 #define L1_RECOVERY 1 // L1 recovery
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	227
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	228
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	229 #if (L1_GPRS == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	230 #define RLC_VERSION RLC_SCENARIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	231 #if (RLC_VERSION == RLC_SCENARIO)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	232 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	233 // output stat on CRC error blocks
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	234 // The user must enter the cs type and
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	235 // the number of frames desired.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	236 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	237 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	238 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	239
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	240 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	241 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	242 // activated by a layer 3 message (BG_TASK_START (<task number>))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	243 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	244 // Warning : Works only with DSP>=31
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	245 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	246 #define DSP_BACKGROUND_TASKS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	247 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	248
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	249 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	250 #define DSP_BACKGROUND_TASKS 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	251 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	252 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	253 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	254
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	255 // Audio tasks selection
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	256 //-----------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	257
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	258 #if (AUDIO_TASK == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	259 #define KEYBEEP 1 // Enable keybeep feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	260 #define TONE 1 // Enable tone feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	261 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	262 #if (OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	263 #define GSMLITE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	264 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	265 #if ((OP_L1_STANDALONE == 1) \|\| (!GSMLITE))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	266 #define MELODY_E1 1 // Enable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	267 #define VOICE_MEMO 1 // Enable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	268
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	269 #define FIR 1 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	270 #if (DSP == 33) \|\| (DSP == 34) \|\| (DSP == 35) \|\| (DSP == 36)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	271 #define AUDIO_MODE 1 // Enable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	272 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	273 #define AUDIO_MODE 0 // Disable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	274 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	275 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	276 #define MELODY_E1 0 // Disable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	277 #define VOICE_MEMO 0 // Disable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	278 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	279 #define FIR 1 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	280 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	281 #define FIR 0 // Disable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	282 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	283
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	284 #define AUDIO_MODE 0 // Disable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	285 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	286 // Define CPORT for ESample only
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	287 #if ((CHIPSET == 12) && ((DSP == 35) \|\| (DSP == 36)))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	288 #define L1_CPORT 1 // Enable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	289 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	290 #define L1_CPORT 0 // Disable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	291 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	292
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	293 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	294 #define KEYBEEP 0 // Enable keybeep feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	295 #define TONE 0 // Enable tone feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	296 #define MELODY_E1 0 // Enable melody format E1 feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	297 #define VOICE_MEMO 0 // Enable voice memorization feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	298
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	299 #define FIR 0 // Enable FIR feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	300 #define AUDIO_MODE 0 // Enable Audio mode feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	301 #define L1_CPORT 0 // Enable cport feature
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	302 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	303
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	304 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO \| MELODY_E2) // audio background task is used by speech reco and melody_e2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	305 #if (OP_RIV_AUDIO == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	306 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	307 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	308
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	309
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	310 // Vocoder selections
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	311 //-------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	312
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	313 #define FR 1 // Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	314 #define FR_HR 2 // Full Rate + Half Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	315 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	316 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	317
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	318 // Standard (frequency plan) selections
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	319 //-------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	320
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	321 #define GSM 1 // GSM900.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	322 #define GSM_E 2 // GSM900 Extended.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	323 #define PCS1900 3 // PCS1900.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	324 #define DCS1800 4 // DCS1800.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	325 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	326 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	327 #define GSM850 7 // GSM850 Band
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	328 #define DUAL_US 8 // PCS1900 + GSM850
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	329
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	330 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	331 /* Power Management */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	332 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	333 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	334
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	335
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	336 /---------------------------------------------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	337 /* DSP configurations */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	338 /* ------------------ */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	339 /* DSP \| FR\| HR\|EFR\|14.4\| SPEED \|12LA68\|12LA68 \|4L32\|AEC\| MCU/DSP */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	340 /* (version) \| \| \| \| \| \|POLE80\|POLE112\| \|/NS\| interface */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	341 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	342 /* 0 (821) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	343 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	344 /* 1 (830) \| x \| \| \| \| 39Mhz \| (1) \| \| x \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	345 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	346 /* 2 (912) \| x \| x \| \| \| 58.5Mhz \| x \| \| \| \| 2 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	347 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	348 /* 3 (10xx) \| x \| \| x \| x \| 65Mhz \| x \| \| \| x \| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	349 /* ----------+---+---+---+----+---------+------+-------+----\|---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	350 /* 4 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \| x \| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	351 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	352 /* 5 (830) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	353 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	354 /* 6 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \|(2)\| 3 */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	355 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	356 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	357 /(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	358 /* not corrected. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	359 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	360 /(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP /
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	361 /* interface which support AEC, therefore AEC is defined as 1. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	362 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	363 /(3) Pole112 include RIF DL correction. No patch is needed if this one only /
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	364 /* include RIF/DL problem. */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	365 /* */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	366 /---------------------------------------------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	367 #if (DSP == 16 \|\| DSP == 17)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	368
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	369 /* #define CLKMOD1 0x414e // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	370 #define CLKMOD2 0x414e // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	371 #define CLKSTART 0x29 // ...65 Mips */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	372
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	373 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	374 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	375 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	376
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	377 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	378 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	379 #define CLKSTART 0x25 // ...39 Mips */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	380
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	381 #define VOC FR_HR_EFR // FR + HR + EFR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	382 #define DATA14_4 1 // No 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	383 #define AEC 1 // AEC/NS supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	384 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	385 #define DSP_START 0x2000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	386 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	387
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	388 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	389
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	390 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	391 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	392 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	393 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	394 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	395
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	396 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	397 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	398 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	399 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	400 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	401 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	402 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	403 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	404
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	405 #elif (DSP == 30) // First GPRS.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	406 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	407 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	408 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	409
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	410 #define VOC FR_HR_EFR // FR + HR + EFR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	411 #define DATA14_4 1 // No 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	412 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	413 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	414 #define DSP_START 0x1F81
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	415 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	416 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	417
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	418 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	419 #elif (DSP == 31) // ROM Code GPRS G0.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	420 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	421 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	422 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	423
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	424 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	425 #define DATA14_4 1 // 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	426 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	427 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	428
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	429 #define DSP_START 0x8763
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	430
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	431 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	432 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	433
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	434 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	435 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	436
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	437 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	438 #elif (DSP == 32) // ROM Code GPRS G1.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	439 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	440 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	441 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	442
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	443 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	444 #define DATA14_4 1 // 14.4 data allowed.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	445 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	446 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	447
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	448 #define DSP_START 0x8763
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	449
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	450 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	451
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	452 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	453 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	454
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	455 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	456 #elif (DSP == 33) // ROM Code GPRS.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	457 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	458 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	459 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	460 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	461 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	462 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	463 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	464 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	465 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	466 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	467 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	468 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	469 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	470 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	471 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	472 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	473 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	474
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	475 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	476
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	477 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	478
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	479 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	480
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	481 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	482 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	483
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	484 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	485
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	486 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	487
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	488 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	489
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	490 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	491
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	492 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	493
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	494 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	495 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	496 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	497
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	498 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	499 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	500 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	501 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	502 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	503
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	504 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	505 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	506
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	507 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	508 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	509
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	510 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	511 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	512
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	513 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	514
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	515 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	516 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	517 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	518 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	519 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	520
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	521 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	522 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	523 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	524
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	525 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	526 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	527 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	528 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	529
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	530 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	531 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	532 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	533 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	534 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	535 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	536 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	537 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	538
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	539 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	540 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	541 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	542 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	543
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	544 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	545 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	546 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	547 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	548 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	549 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	550
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	551 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	552 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	553
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	554 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	555 #define DSP_DEBUG_GSM_MASK 0x0000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	556 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	557 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	558
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	559 #if DCO_ALGO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	560 // DCO type of scheduling
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	561 #define C_CN_DCO_PARAM 0xA248
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	562 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	563
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	564 #elif (DSP == 34) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	565 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	566 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	567 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	568 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	569 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	570 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	571 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	572 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	573 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	574 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	575 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	576 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	577 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	578 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	579 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	580 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	581 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	582 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	583
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	584 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	585
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	586 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	587
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	588 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	589 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	590
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	591 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	592
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	593 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	594
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	595 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	596
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	597 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	598
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	599 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	600
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	601 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	602 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	603 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	604
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	605 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	606 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	607 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	608 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	609 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	610 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	611 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	612
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	613 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	614 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	615
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	616 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	617 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	618
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	619 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	620
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	621 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	622 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	623 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	624 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	625 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	626
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	627 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	628 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	629 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	630
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	631 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	632 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	633 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	634 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	635
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	636 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	637 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	638 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	639 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	640 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	641 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	642 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	643 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	644
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	645 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	646 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	647 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	648 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	649
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	650 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	651 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	652 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	653
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	654 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	655 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	656
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	657 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	658 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	659 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	660
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	661 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	662 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	663
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	664 // masks to apply on d_error_status bit field
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	665 #define DSP_DEBUG_GSM_MASK 0x0000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	666 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	667 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	668
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	669 #elif (DSP == 35) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	670 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	671 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	672 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	673 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	674 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	675 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	676 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	677 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	678 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	679 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	680 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	681 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	682 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	683 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	684 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	685 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	686 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	687 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	688
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	689 #define FF_L1_TCH_VOCODER_CONTROL 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	690 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	691
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	692 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	693
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	694 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	695
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	696 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	697 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	698
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	699 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	700
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	701 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	702
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	703 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	704
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	705 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	706
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	707 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	708
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	709 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	710 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	711 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	712
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	713 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	714 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	715 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	716 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	717 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	718 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	719 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	720
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	721 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	722 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	723
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	724 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	725 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	726
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	727 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	728
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	729 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	730 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	731 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	732 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	733 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	734
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	735 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	736 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	737 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	738
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	739 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	740 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	741 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	742 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	743
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	744 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	745 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	746 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	747 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	748 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	749 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	750 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	751 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	752
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	753 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	754 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	755 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	756 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	757
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	758 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	759 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	760 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	761
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	762 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	763 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	764
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	765 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	766 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	767 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	768
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	769 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	770 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	771
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	772 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	773 #define DSP_DEBUG_GSM_MASK 0x08BD
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	774 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	775 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	776 #elif (DSP == 36) // ROM Code GPRS AMR.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	777 #define CLKMOD1 0x4006 // ...
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	778 #define CLKMOD2 0x4116 // ...65 Mips pll free
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	779 #define CLKSTART 0x29 // ...65 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	780 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	781 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	782 #define AEC 1 // AEC/NS not supported.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	783 #if (OP_RIV_AUDIO == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	784 #define L1_NEW_AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	785 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	786 // Available but not yet tuned with Riviera AUDIO
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	787 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	788 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	789 #if ((L1_NEW_AEC) && (!AEC))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	790 // First undef the flag to avoid warnings at compilation time
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	791 #undef AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	792 #define AEC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	793 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	794 #define MAP 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	795 #undef L1_AMR_NSYNC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	796 #define L1_AMR_NSYNC 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	797 #define FF_L1_TCH_VOCODER_CONTROL 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	798 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	799
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	800 #define DSP_START 0x7000
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	801
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	802 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	803
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	804 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	805 #define ULYSSE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	806
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	807 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	808
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	809 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	810
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	811 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	812
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	813 // management.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	814
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	815 // DSP_IDLE3 is not supported in simulation
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	816
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	817 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	818 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	819 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	820
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	821 // DSP software work-around config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	822 // bit0 - Work-around to support CRTG.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	823 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	824 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	825 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	826 #if (ANALOG == 1) // OMEGA / NAUSICA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	827 #define C_DSP_SW_WORK_AROUND 0x0006
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	828
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	829 #elif (ANALOG == 2) // IOTA
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	830 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	831
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	832 #elif (ANALOG == 3) // SYREN
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	833 #define C_DSP_SW_WORK_AROUND 0x000E
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	834 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	835
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	836 // This workaround should be enabled only for H2-sample on full build config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	837 #if (OP_L1_STANDALONE==1)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	838 #define RAZ_VULSWITCH_REGAUDIO 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	839 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	840
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	841 /* DSP debug trace configuration */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	842 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	843 #if (MELODY_E2)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	844 // In case of the melody E2 the DSP trace must be disable because the
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	845 // melody instrument waves are overlayed with DSP trace buffer
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	846
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	847 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	848 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	849 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	850
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	851 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	852 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	853 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	854 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	855
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	856 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	857 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	858 // Currently not supported !
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	859 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	860 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	861 // DSP debug trace API buufer config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	862 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	863 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	864
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	865 // DSP debug trace type config
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	866 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	867 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	868 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	869
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	870 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	871 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	872 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	873
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	874 // AMR trace
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	875 #define C_AMR_TRACE_ID 55
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	876
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	877 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	878 /* d_error_status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	879 /-------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	880
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	881 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	882 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	883
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	884 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	885 #define DSP_DEBUG_GSM_MASK 0x08BD
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	886 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	887 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	888 #endif // DSP
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	889
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	890 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	891 /* Default value */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	892 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	893 #ifndef W_A_DSP1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	894 #define W_A_DSP1 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	895 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	896
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	897 #ifndef DATA14_4
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	898 #define DATA14_4 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	899 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	900
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	901 #ifndef W_A_ITFORCE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	902 #define W_A_ITFORCE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	903 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	904
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	905 #ifndef W_A_DSP_IDLE3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	906 #define W_A_DSP_IDLE3 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	907 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	908
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	909 #ifndef L1_NEW_AEC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	910 #define L1_NEW_AEC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	911 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	912
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	913 #ifndef DSP_DEBUG_TRACE_ENABLE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	914 #define DSP_DEBUG_TRACE_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	915 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	916
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	917 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	918 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	919 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	920
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	921 #ifndef D_ERROR_STATUS_TRACE_ENABLE
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	922 #define D_ERROR_STATUS_TRACE_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	923 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	924
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	925 #ifndef L1_GTT
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	926 #define L1_GTT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	927 #define TTY_SYNC_MCU 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	928 #define TTY_SYNC_MCU_2 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	929 #define L1_GTT_FIFO_TEST_ATOMIC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	930 #define NEW_WKA_PATCH 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	931 #define OPTIMISED 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	932 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	933
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	934 #ifndef L1_AMR_NSYNC
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	935 #define L1_AMR_NSYNC 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	936 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	937
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	938 #ifndef FF_L1_TCH_VOCODER_CONTROL
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	939 #define FF_L1_TCH_VOCODER_CONTROL 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	940 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	941 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	942
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	943 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	944 /* Download */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	945 /------------------------------------/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	946
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	947
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	948 /* Possible values for the download status */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	949
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	950 #define LEAD_READY 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	951 #define BLOCK_READY 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	952 #define PROGRAM_DONE 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	953 #define PAGE_SELECTION 4
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	954
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	955
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	956 /************************************/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	957 /* Options of compilation... */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	958 /************************************/
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	959
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	960 // Possible choice of hardware plateform.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	961 #define GEMINI 1 // GEMINI chip (rom dsp code)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	962 #define POLESTAR 2 // POLESTAR chip (no rom)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	963
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	964 // Possible choice for DSP software setup.
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	965 #define NO_DWNLD 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	966 #define PATCH_DWNLD 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	967 #define DSP_DWNLD 2
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	968 #define PATCH_DSP_DWNLD 3
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	969
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	970 // MAC-S status reporting to Layer 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	971 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	972
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	973
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	974 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	975 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	976
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	977 //---------------------------------------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	978
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	979 // Neighbor Cell RXLEV indication
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	980 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	981 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	982 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	983 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	984 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	985
1e41550feec5 nuc-fw: Init_Target() reconstructed Michael Spacefalcon <msokolov@ivan.Harhan.ORG> parents: diff changeset	986 #endif /* __L1_CONFG_H__ */

FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/L1/include/l1_confg.h @ 356:4e0aa166baa5