FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/init_target.c @ 421:4f8a9b2229e9
loadtool.help: updates for Compal target support
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Thu, 19 Jun 2014 00:23:28 +0000 |
parents | afceeeb2cba1 |
children | 98c6be4d3d8d |
rev | line source |
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1 /* |
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2 * Init_Target() is the first function called from Application_Initialize(). |
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3 * But unfortunately, our TCS211 semi-src has this function in a binary lib. |
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4 * I was able to find a conditioned-out version in the LoCosto source that |
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5 * seems to be a fit - so I'm going to massage it a bit to match the sequence |
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6 * of operations seen in the disassembly of our reference binary. |
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7 */ |
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8 |
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9 #include "../include/config.h" |
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10 #include "../include/sys_types.h" |
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11 |
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12 #include "mem.h" |
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13 #include "clkm.h" |
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14 #include "armio.h" |
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15 #include "dma.h" |
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16 #include "timer.h" |
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17 #include "inth.h" |
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18 #include "iq.h" |
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19 #include "rhea_arm.h" |
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20 #include "ulpd.h" |
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21 |
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22 #if !CONFIG_GSM |
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23 #include "timer2.h" |
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24 #endif |
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25 |
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26 /* TPU_FREEZE is defined in l1_const.h */ |
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27 #include "../L1/include/l1_confg.h" |
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28 #include "../L1/include/l1_const.h" |
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29 |
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30 void Init_Target(void) |
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31 { |
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32 #if 1 //(PSP_STANDALONE == 0) |
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33 // RIF/SPI rising edge clock for ULYSSE |
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34 //-------------------------------------------------- |
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35 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) |
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36 #if ((CHIPSET >= 3)) |
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37 #if (CHIPSET == 12) |
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38 F_CONF_RIF_RX_RISING_EDGE; |
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39 F_CONF_SPI_RX_RISING_EDGE; |
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40 #elif (CHIPSET == 15) |
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41 //do the DRP init here for Locosto |
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42 #if (L1_DRP == 1) |
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43 // drp_power_on(); This should be done after the script is downloaded. |
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44 #endif |
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45 #else |
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46 #if (BOARD==35) |
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47 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000; |
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48 #elif CONFIG_TARGET_PIRELLI // from disasm of original fw |
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49 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050; |
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50 #else |
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51 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000; |
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52 #endif /* (BOARD == 35) */ |
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53 #endif |
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54 #endif |
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55 #endif /* ANLG(ANALOG)) */ |
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56 |
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57 #if 0 //(OP_L1_STANDALONE == 1) |
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58 #if (BOARD == 40) || (BOARD == 41) || \ |
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59 (BOARD == 42) || (BOARD == 43) || (BOARD == 45) |
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60 // enable 8 Ohm amplifier for audio on D-sample |
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61 AI_ConfigBitAsOutput (1); |
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62 AI_SetBit(1); |
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63 #elif (BOARD == 70) || (BOARD == 71) |
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64 //Locosto I-sample or UPP costo board.BOARD |
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65 // Initialize the ARMIO bits as per the I-sample spec |
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66 // FIXME |
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67 #endif |
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68 #endif /* (OP_L1_STANDALONE == 1) */ |
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69 #endif /* PSP_STANDALONE ==0 */ |
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70 |
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71 // Watchdog |
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72 //-------------------------------------------------- |
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73 TM_DisableWatchdog(); /* Disable Watchdog */ |
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74 #if (CHIPSET == 12) || (CHIPSET == 15) |
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75 TM_SEC_DisableWatchdog(); |
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76 #endif |
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77 |
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78 freecalypso_disable_bootrom_pll(); |
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79 |
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80 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) |
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81 |
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82 /* |
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83 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules |
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84 */ |
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85 // IRQ, Timer and bridge may SLEEP |
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86 // In first step, same configuration as SAMSON |
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87 //-------------------------------------------------- |
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88 #if (CHIPSET == 12) |
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89 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS); |
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90 #elif (CHIPSET == 15) |
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91 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/ |
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92 |
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93 #else |
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94 CLKM_CNTL_OR(CLKM_IRQ_DIS | CLKM_TIMER_DIS); |
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95 |
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96 // Select VTCXO input frequency |
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97 //-------------------------------------------------- |
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98 CLKM_UNUSED_VTCXO_26MHZ; |
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99 |
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100 // Rita RF uses 26MHz VCXO |
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101 #if (RF_FAM == 12) |
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102 CLKM_USE_VTCXO_26MHZ; |
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103 #endif |
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104 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB |
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105 #if (RF_FAM == 43) && (BOARD == 46) |
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106 CLKM_USE_VTCXO_26MHZ; |
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107 #endif |
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108 #endif |
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109 |
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110 // Control HOM/SAM automatic switching |
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111 //-------------------------------------------------- |
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112 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG; |
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113 |
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114 /* |
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115 * Disassembly of Init_Target() in init.obj in main.lib in the |
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116 * Leonardo reference version reveals that the code does the |
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117 * following at this point: |
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118 */ |
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119 RHEA_INITRHEA(0,0,0xFF); |
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120 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); |
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121 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); |
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122 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ |
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123 /* at this point the original code sets up the memory wait states */ |
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124 /* we'll do it differently */ |
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125 RHEA_INITAPI(0,1); |
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126 RHEA_INITARM(0,0); |
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127 DPLL_SET_PLL_ENABLE; |
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128 |
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129 /* |
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130 * Disable and Clear all pending interrupts |
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131 */ |
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132 #if (CHIPSET == 12) || (CHIPSET == 15) |
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133 F_INTH_DISABLE_ALL_IT; // MASK all it |
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134 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ |
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135 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ |
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136 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ |
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137 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source |
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138 #else |
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139 INTH_DISABLEALLIT; |
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140 INTH_RESETALLIT; |
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141 INTH_CLEAR; /* reset IRQ/FIQ source */ |
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142 #endif |
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143 |
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144 // INTH |
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145 //-------------------------------------------------- |
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146 #if (CHIPSET == 12) || (CHIPSET == 15) |
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147 #if (GSM_IDLE_RAM != 0) |
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148 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers |
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149 #else |
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150 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers |
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151 #endif |
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152 #else |
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153 IQ_SetupInterrupts(); |
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154 #endif |
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155 |
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156 // DMA |
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157 //-------------------------------------------------- |
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158 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same |
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159 #if 1 //(OP_L1_STANDALONE == 0) |
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160 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX |
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161 #endif |
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162 |
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163 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */ |
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164 |
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165 #else |
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166 |
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167 // RHEA Bridge |
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168 //-------------------------------------------------- |
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169 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F |
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170 RHEA_INITRHEA(0,0,0x7F); |
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171 |
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172 #if (CHIPSET == 6) |
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173 // WS_H = 1 , WS_L = 15 |
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174 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz |
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175 #else |
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176 // WS_H = 0 , WS_L = 7 |
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177 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz |
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178 #endif |
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179 |
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180 // Write_en_0 = 0 , Write_en_1 = 0 |
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181 RHEA_INITARM(0,0); |
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182 |
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183 // INTH |
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184 //-------------------------------------------------- |
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185 INTH_DISABLEALLIT; // MASK all it |
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186 INTH_CLEAR; // reset IRQ/FIQ source |
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187 IQ_SetupInterrupts(); |
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188 |
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189 // DMA |
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190 //-------------------------------------------------- |
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191 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same |
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192 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead) |
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193 |
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194 #if (CHIPSET == 6) |
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195 // Memory WS configuration for ULYSS/G1 (26 Mhz) board |
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196 //----------------------------------------------------- |
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197 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0); |
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198 #endif |
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199 |
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200 // CLKM |
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201 //-------------------------------------------------- |
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202 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */ |
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203 |
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204 #if (CHIPSET == 6) |
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205 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26); |
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206 #else |
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207 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS); |
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208 #endif |
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209 |
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210 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */ |
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211 |
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212 // Freeze ULPD timer .... |
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213 //-------------------------------------------------- |
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214 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0; |
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215 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE; |
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216 |
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217 // reset INC_SIXTEEN and INC_FRAC |
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218 //-------------------------------------------------- |
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219 #if 0 //(OP_L1_STANDALONE == 1) |
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220 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE); |
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221 #else |
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222 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133 |
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223 // 26000 --> 166 |
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224 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845 |
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225 // 26000 --> 43691 |
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226 #endif /* OP_L1_STANDALONE */ |
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227 |
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228 // program ULPD WAKE-UP .... |
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229 //================================================= |
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230 #if (CHIPSET == 2) |
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231 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame |
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232 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods |
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233 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods |
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234 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods |
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235 #else |
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236 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames |
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237 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods |
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238 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods |
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diff
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239 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods |
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240 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods |
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241 #endif |
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242 |
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243 #if (CHIPSET == 15) |
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244 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0 |
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245 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto |
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246 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ |
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247 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ |
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248 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN |
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249 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN |
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diff
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250 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK |
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251 #endif |
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252 |
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253 // Set Gauging versus HF (PLL) |
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254 //================================================= |
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255 ULDP_GAUGING_SET_HF; // Enable gauging versus HF |
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256 ULDP_GAUGING_HF_PLL; // Gauging versus PLL |
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257 |
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258 // current supply for quartz oscillation |
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259 //================================================= |
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260 #if 0 //(OP_L1_STANDALONE == 1) |
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261 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value |
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262 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27; |
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263 #endif |
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parents:
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264 #else |
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265 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41)) |
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diff
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266 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27; |
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267 #elif (BOARD == 7) |
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diff
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268 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24; |
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269 #endif |
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270 #endif /* OP_L1_STANDALONE */ |
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271 |
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272 // stop Gauging if any (debug purpose ...) |
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273 //-------------------------------------------------- |
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274 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN) |
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275 { |
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276 volatile int j; |
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diff
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277 ULDP_GAUGING_STOP; /* Stop the gauging */ |
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diff
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278 /* wait for gauging it*/ |
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diff
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279 // one 32khz period = 401 periods of 13Mhz |
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280 for (j=1; j<50; j++); |
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281 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING); |
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parents:
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282 } |
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283 |
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284 #if 1 //(OP_L1_STANDALONE == 0) |
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diff
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285 AI_ClockEnable (); |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
286 |
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287 #if (BOARD == 7) |
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diff
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288 // IOs configuration of the B-Sample in order to optimize the power consumption |
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diff
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289 AI_InitIOConfig(); |
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diff
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290 |
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291 // Set LPG instead of DSR_MODEM |
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292 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40; |
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parents:
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293 // Reset the PERM_ON bit of LCR_REG |
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diff
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294 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80); |
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parents:
diff
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295 #elif ((BOARD == 8) || (BOARD == 9)) |
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parents:
diff
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296 // IOs configuration of the C-Sample in order to optimize the power consumption |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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297 AI_InitIOConfig(); |
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parents:
diff
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|
298 |
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299 // set the debug latch to 0x00. |
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parents:
diff
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300 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00; |
1e41550feec5
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parents:
diff
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301 #elif ((BOARD == 35) || (BOARD == 46)) |
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parents:
diff
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|
302 AI_InitIOConfig(); |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
303 // CSMI INTERFACE |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
304 // Initialize CSMI clients for GSM control |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
305 // and Fax/Data services |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
306 CSMI_Init(); |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
307 GC_Initialize(); // GSM control initialization |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
308 CU_Initialize(); // Trace initialization |
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parents:
diff
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|
309 CF_Initialize(); // Fax/Data pre-initialization |
1e41550feec5
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parents:
diff
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|
310 #elif ((BOARD == 40) || (BOARD == 41)) |
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parents:
diff
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|
311 // IOs configuration of the D-Sample in order to optimize the power consumption |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
312 AI_InitIOConfig(); |
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parents:
diff
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|
313 |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
314 #ifdef BTEMOBILE |
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parents:
diff
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|
315 // Reset BT chip by toggling the Island's nRESET_OUT signal |
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parents:
diff
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|
316 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04; |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
317 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4); |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
318 #endif |
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parents:
diff
changeset
|
319 |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
320 #if 0 // FreeCalypso |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
321 // set the debug latch to 0x0000. |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
322 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
323 #endif |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
324 #elif ((BOARD == 70) || (BOARD == 71)) |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
325 AI_InitIOConfig(); |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
326 /* Mark The System configuration According to I-Sample */ |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
327 /* Adding GPIO Mux Setting Here */ |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
328 pin_configuration_all(); // Init Tuned for Power Management |
1e41550feec5
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parents:
diff
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|
329 /* A22 is Enabled in int.s hence not Here */ |
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parents:
diff
changeset
|
330 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */ |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
331 |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
332 /* Add code to find out the manufacture id of NOR flash*/ |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
333 |
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nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
334 // Copy ffsdrv_device_id_read() function code to RAM. The only known |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
335 // way to determine the size of the code is to look either in the |
1e41550feec5
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parents:
diff
changeset
|
336 // linker-generated map file or in the assember output file. |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
337 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code, |
1e41550feec5
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parents:
diff
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|
338 (UWORD16 *) &ffsdrv_device_id_read, |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
339 sizeof(detect_code)); |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
340 |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
341 // Combine bit 0 of the thumb mode function pointer with the address |
1e41550feec5
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parents:
diff
changeset
|
342 // of the code in RAM. Then call the detect function in RAM. |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
343 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code); |
1e41550feec5
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
344 (*myfp)(0x06000000, &manufact, device_id); |
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345 |
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346 enable_ps_ram_burst(); |
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347 |
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348 if( 0x7e == device_id[0] ) |
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349 { |
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350 enable_flash_burst(); |
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351 flash_device_id = 0x7E; |
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352 } |
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353 else |
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354 { |
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355 enable_flash_burst_mirror(); |
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356 flash_device_id = 0; |
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357 } |
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358 |
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359 /* FreeCalypso: a bunch of dead code cut out */ |
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360 |
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361 #endif // BOARD |
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362 |
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363 // Enable HW Timers 1 & 2 |
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364 TM_EnableTimer (1); |
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365 TM_EnableTimer (2); |
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366 |
131
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367 #if !CONFIG_GSM |
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368 Dtimer2_Init_cntl (1875, 1, 0, 1); |
136
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369 Dtimer2_Start (1); |
131
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370 #endif |
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371 |
115
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372 #endif /* (OP_L1_STANDALONE == 0) */ |
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373 |
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374 } |
131
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375 |
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376 /* |
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377 * Init_Unmask_IT() is the last function called from Application_Initialize(); |
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378 * it also had to be reconstructed from disassembly. |
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379 */ |
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380 |
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381 void Init_Unmask_IT(void) |
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382 { |
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383 #if CONFIG_GSM |
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384 IQ_Unmask(IQ_FRAME); |
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385 #endif |
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386 IQ_Unmask(IQ_UART_IRDA_IT); |
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387 IQ_Unmask(IQ_UART_IT); |
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388 #if 0 |
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389 IQ_Unmask(IQ_ARMIO); |
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390 IQ_Unmask(IQ_API); |
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391 #endif |
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392 #if !CONFIG_GSM |
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393 IQ_Unmask(IQ_TIM2); |
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394 #endif |
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395 } |