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annotate gsm-fw/bsp/abb+spi/spi_drv.h @ 761:55a84763c417

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author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 11 Oct 2014 23:00:04 +0000
parents cc0944d35698
children
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1 /******************************************************************************/
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
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3 /* */
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This*/
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6 /* product is protected under copyright law and trade secret law as an*/
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All*/
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8 /* rights reserved. */
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9 /* */
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10 /* */
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11 /* Filename : spi_drv.h */
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12 /* */
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13 /* Description : SPI registers and bits definitions. */
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14 /* Functions and macros to drive the SPI module. */
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15 /* The Serial Port Interface is a bidirectional 3 lines */
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16 /* interface dedicated to the transfer of data to and */
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17 /* from up to 5 external devices offering a 3 lines */
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18 /* serial interface. */
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19 /* In this project, it is only used to connect the TI */
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20 /* Analog BaseBand (ABB). */
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21 /* It is assumed that the ABB is connected as the SPI */
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22 /* device 0. */
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23 /* */
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24 /* This interface is specified to be compatible with */
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25 /* the UMA1018M Philips, the FUJITSU MB15F02, the */
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26 /* SIEMENS PMB2306T synthesizers and the TI ABB. */
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27 /* */
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28 /* This serial port is based on a looped shift-register */
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29 /* thus allowing both transmit (PISO) and receive (SIPO) */
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30 /* modes. */
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31 /* */
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32 /* */
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33 /* Author : Pascal PUEL */
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34 /* */
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35 /* Version number : 1.28 */
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36 /* */
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37 /* Date and time : 07/01/03 */
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38 /* */
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39 /* Previous delta : Rework */
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40 /* */
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41 /******************************************************************************/
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42
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43 #ifndef __SPI_DRV_H__
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44 #define __SPI_DRV_H__
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45
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46 #include "../../include/config.h"
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47 #include "../../include/sys_types.h"
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48
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49 #include "../mem.h"
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50
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51 // SPI module registers definition
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52 #define SPI_REG_SET1 (MEM_SPI + 0x00)
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53 #define SPI_REG_SET2 (MEM_SPI + 0x02)
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54 #define SPI_REG_CTRL (MEM_SPI + 0x04)
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55 #define SPI_REG_STATUS (MEM_SPI + 0x06)
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56 #define SPI_REG_TX_LSB (MEM_SPI + 0x08)
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57 #define SPI_REG_TX_MSB (MEM_SPI + 0x0A)
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58 #define SPI_REG_RX_LSB (MEM_SPI + 0x0C)
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59 #define SPI_REG_RX_MSB (MEM_SPI + 0x0E)
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60
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61
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62 // SPI module bits definition of register SPI_REG_SET1
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63 #define SPI_CLK_OFF 0x0000 // default value
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64 #define SPI_CLK_ON 0x0001
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65 #define SPI_CLOCK_DIV_1 0x0000 // default value
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66 #define SPI_CLOCK_DIV_2 0x0002
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67 #define SPI_CLOCK_DIV_4 0x0004
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68 #define SPI_CLOCK_DIV_8 0x0006
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69 #define SPI_CLOCK_DIV_16 0x0008
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70 #if (CHIPSET == 12)
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71 #define SPI_CLOCK_DIV_32 0x000A
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72 #define SPI_CLOCK_DIV_64 0x000C
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73 #define SPI_CLOCK_DIV_128 0x000E
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74 #endif
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75 #define SPI_IT_MASK_0 0x0010 // default value
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76 #define SPI_IT_DEMASK_0 0x0000
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77 #define SPI_IT_MASK_1 0x0020 // default value
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78 #define SPI_IT_DEMASK_1 0x0000
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79
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81 // SPI module bits definition of register SPI_REG_SET2
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82 #define SPI_CLK_EDG_FALL 0x0000 // default value for device 0
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83 #define SPI_CLK_EDG_RISE 0x0001
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84 #define SPI_CLK_EDG_FALL_1 0x0000 // default value for device 1
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85 #define SPI_CLK_EDG_RISE_1 0x0002
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86 #define SPI_CLK_EDG_FALL_2 0x0000 // default value for device 2
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87 #define SPI_CLK_EDG_RISE_2 0x0004
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88 #define SPI_CLK_EDG_FALL_3 0x0000 // default value for device 3
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89 #define SPI_CLK_EDG_RISE_3 0x0008
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90 #define SPI_CLK_EDG_FALL_4 0x0000 // default value for device 4
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91 #define SPI_CLK_EDG_RISE_4 0x0010
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92 #define SPI_NTSPEN_NEG_LEV 0x0000 // default value for device 0
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93 #define SPI_NTSPEN_POS_LEV 0x0020
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94 #define SPI_NTSPEN_NEG_LEV_1 0x0000 // default value for device 1
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95 #define SPI_NTSPEN_POS_LEV_1 0x0040
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96 #define SPI_NTSPEN_NEG_LEV_2 0x0000 // default value for device 2
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97 #define SPI_NTSPEN_POS_LEV_2 0x0080
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98 #define SPI_NTSPEN_NEG_LEV_3 0x0000 // default value for device 3
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99 #define SPI_NTSPEN_POS_LEV_3 0x0100
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100 #define SPI_NTSPEN_NEG_LEV_4 0x0000 // default value for device 4
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101 #define SPI_NTSPEN_POS_LEV_4 0x0200
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102 #define SPI_NTSPEN_LEV_TRIG 0x0000 // default value for device 0
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103 #define SPI_NTSPEN_EDG_TRIG 0x0400
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104 #define SPI_NTSPEN_LEV_TRIG_1 0x0000 // default value for device 1
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105 #define SPI_NTSPEN_EDG_TRIG_1 0x0800
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106 #define SPI_NTSPEN_LEV_TRIG_2 0x0000 // default value for device 2
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107 #define SPI_NTSPEN_EDG_TRIG_2 0x1000
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108 #define SPI_NTSPEN_LEV_TRIG_3 0x0000 // default value for device 3
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109 #define SPI_NTSPEN_EDG_TRIG_3 0x2000
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110 #define SPI_NTSPEN_LEV_TRIG_4 0x0000 // default value for device 4
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111 #define SPI_NTSPEN_EDG_TRIG_4 0x4000
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112
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113
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114 // SPI module bits definition of register SPI_REG_CTRL
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115 #define SPI_RDWR_DEACTIV 0x0000 // default value
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116 #define SPI_RDWR_ACTIV 0x0001
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117 #define SPI_WR_DEACTIV 0x0000 // default value
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118 #define SPI_WR_ACTIV 0x0002
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119 #define SPI_WNB_0 0x0000 // default value
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120 #define SPI_WNB_1 0x0004
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121 #define SPI_WNB_2 0x0008
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122 #define SPI_WNB_3 0x000c
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123 #define SPI_WNB_4 0x0010
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124 #define SPI_WNB_5 0x0014
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125 #define SPI_WNB_6 0x0018
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126 #define SPI_WNB_7 0x001c
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127 #define SPI_WNB_8 0x0020
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128 #define SPI_WNB_9 0x0024
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129 #define SPI_WNB_10 0x0028
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130 #define SPI_WNB_11 0x002c
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131 #define SPI_WNB_12 0x0030
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132 #define SPI_WNB_13 0x0034
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133 #define SPI_WNB_14 0x0038
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134 #define SPI_WNB_15 0x003c
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135 #define SPI_WNB_16 0x0040
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136 #define SPI_WNB_17 0x0044
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137 #define SPI_WNB_18 0x0048
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138 #define SPI_WNB_19 0x004c
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139 #define SPI_WNB_20 0x0050
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140 #define SPI_WNB_21 0x0054
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141 #define SPI_WNB_22 0x0058
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142 #define SPI_WNB_23 0x005c
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143 #define SPI_WNB_24 0x0060
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144 #define SPI_WNB_25 0x0064
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145 #define SPI_WNB_26 0x0068
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146 #define SPI_WNB_27 0x006c
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147 #define SPI_WNB_28 0x0070
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148 #define SPI_WNB_29 0x0074
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149 #define SPI_WNB_30 0x0078
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150 #define SPI_WNB_31 0x007c
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151
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152
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153 // SPI possible device IDs
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154 #define SPI_DEV0 0x0000
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155 #define SPI_DEV1 0x0080
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156 #define SPI_DEV2 0x0100
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157 #define SPI_DEV3 0x0180
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158 #define SPI_DEV4 0x0200
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159
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160 // ABB should be mapped as device 0
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161 #define ABB SPI_DEV0
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162
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163
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164 // SPI module bits definition of register SPI_REG_STATUS
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165 #define RE_ST 0x0001 // bit 0
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166 #define WE_ST 0x0002 // bit 1
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167
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168
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169 /* The ARM emulator requires the spi clock always ON to be able to access */
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170 /* spi registers through a window.*/
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171 /* But it's better to stop the SPI clock in the GSM application to reduce the power consumption. */
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172 /* Validate the next line to reduce power consumption */
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173 //#define SPI_CLK_LOW_POWER
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174
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175
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176
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177 // STRUCTURES
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178 typedef struct
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179 {
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180 SYS_UWORD16 PrescVal;
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181 SYS_UWORD16 DataTrLength;
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182 SYS_UWORD16 DevAddLength;
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183 SYS_UWORD16 DevId;
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184 SYS_UWORD16 ClkEdge;
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185 SYS_UWORD16 TspEnLevel;
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186 SYS_UWORD16 TspEnForm;
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187 }T_SPI_DEV; // T_SPI_DEV is used to define an SPI device
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188
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189
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190 // MACROS
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191 #define SPI_WRITE_TX_LSB(TxLsb) { \
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192 * (volatile SYS_UWORD16 *) SPI_REG_TX_LSB = TxLsb; }
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193
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194 #define SPI_WRITE_TX_MSB(TxMsb) { \
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195 * (volatile SYS_UWORD16 *) SPI_REG_TX_MSB = TxMsb; }
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196
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197 #define SPI_START_WRITE {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_WR_ACTIV; }
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198
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199 #define SPI_START_READ {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_RDWR_ACTIV; }
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200
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201 #define SPI_CLK_DISABLE { \
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202 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_CLK_ON; }
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203
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204 #define SPI_CLK_ENABLE { \
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205 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_CLK_ON; }
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206
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207 #define SPI_MaskIT_WR { \
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208 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_0; }
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209
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210 #define SPI_MaskIT_RD { \
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211 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_1; }
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212
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213 #define SPI_Mask_All_IT { \
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214 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_IT_MASK_0 | SPI_IT_MASK_1); }
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215
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216 #define SPI_UnmaskIT_WR { \
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217 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_0; }
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218
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219 #define SPI_UnmaskIT_RD { \
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220 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_1; }
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221
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222 #define SPI_Unmask_All_IT { \
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223 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~(SPI_IT_MASK_0 | SPI_IT_MASK_1); }
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224
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225 #define SPI_Ready_for_WR { \
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226 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0); }
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227
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228 #define SPI_Ready_for_RD { \
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229 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_1); }
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230
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231 #define SPI_Ready_for_RDWR { \
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232 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0 | SPI_IT_MASK_1); }
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233
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234
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235
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236 // INLINE FUNCTIONS
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237 /*-----------------------------------------------------------------------*/
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238 /* SPI_ReadRX_LSB() */
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239 /* */
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240 /* This function returns the value of SPI_REG_RX_LSB register */
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241 /* */
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242 /*-----------------------------------------------------------------------*/
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243 static inline SYS_UWORD16 SPI_ReadRX_LSB(void)
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244 {
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245 return * (volatile SYS_UWORD16 *) SPI_REG_RX_LSB;
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246 }
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247
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248
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249 /*-----------------------------------------------------------------------*/
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250 /* SPI_ReadRX_MSB() */
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251 /* */
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252 /* This function returns the value of SPI_REG_RX_MSB register */
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253 /* */
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254 /*-----------------------------------------------------------------------*/
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255 static inline SYS_UWORD16 SPI_ReadRX_MSB(void)
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256 {
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257 return * (volatile SYS_UWORD16 *) SPI_REG_RX_MSB;
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258 }
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259
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260
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261
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262 /*-----------------------------------------------------------------------*/
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263 /* SPI_ReadStatus() */
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264 /* */
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265 /* This function returns the value of SPI_REG_STATUS register */
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266 /* */
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267 /*-----------------------------------------------------------------------*/
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268 static inline SYS_UWORD16 SPI_ReadStatus(void)
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269 {
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270 return * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
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271 }
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272
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273
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274
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275 // PROTOTYPES
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276 void SPI_InitDev(T_SPI_DEV *Device);
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277
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278 #endif // __SPI_DRV_H__