FreeCalypso > hg > freecalypso-sw
annotate target-utils/include/ns16550.h @ 53:604648026e9c
fc-xram: baud rate switching implemented per original intent
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 23 Jun 2013 05:16:47 +0000 |
parents | 40f607bb0a2c |
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rev | line source |
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1 #ifndef __NS16550_H |
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2 #define __NS16550_H |
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3 |
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4 /* NS16550 registers */ |
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5 #define NS16550_RBR 0 |
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6 #define NS16550_THR 0 |
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7 #define NS16550_IER 1 |
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8 #define NS16550_IIR 2 |
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9 #define NS16550_FCR 2 |
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10 #define NS16550_LCR 3 |
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11 #define NS16550_MCR 4 |
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12 #define NS16550_LSR 5 |
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13 #define NS16550_MSR 6 |
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14 #define NS16550_SCR 7 |
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15 #define NS16550_DLL 0 |
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16 #define NS16550_DLM 1 |
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17 |
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18 #ifndef __ASSEMBLER__ |
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19 #include "types.h" |
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20 |
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21 struct ns16550_regs { |
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22 u8 datareg; |
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23 u8 ier; |
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24 u8 iir_fcr; |
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25 u8 lcr; |
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26 u8 mcr; |
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27 u8 lsr; |
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28 u8 msr; |
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29 u8 scr; |
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30 }; |
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31 #endif |
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32 |
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33 /* IER bits */ |
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34 #define NS16550_IER_EDSSI 0x08 |
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35 #define NS16550_IER_ELSI 0x04 |
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36 #define NS16550_IER_ETBEI 0x02 |
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37 #define NS16550_IER_ERBFI 0x01 |
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38 |
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39 /* IIR bits */ |
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40 #define NS16550_IIR_FIFOEN 0xC0 |
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41 #define NS16550_IIR_INTID 0x0E |
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42 #define NS16550_IIR_INT_RLS 0x06 |
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43 #define NS16550_IIR_INT_RDA 0x04 |
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44 #define NS16550_IIR_INT_CTO 0x0C |
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45 #define NS16550_IIR_INT_THRE 0x02 |
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46 #define NS16550_IIR_INT_MODEM 0x00 |
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47 #define NS16550_IIR_INTPEND 0x01 |
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48 |
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49 /* FCR bits */ |
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50 |
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51 #define NS16550_FCR_RXTR 0xC0 |
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52 #define NS16550_FCR_RXTR_1 0x00 |
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53 #define NS16550_FCR_RXTR_4 0x40 |
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54 #define NS16550_FCR_RXTR_8 0x80 |
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55 #define NS16550_FCR_RXTR_14 0xC0 |
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56 #define NS16550_FCR_DMAMODE 0x08 |
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57 #define NS16550_FCR_TXRST 0x04 |
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58 #define NS16550_FCR_RXRST 0x02 |
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59 #define NS16550_FCR_FIFOEN 0x01 |
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60 |
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61 /* LCR bits */ |
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62 #define NS16550_LCR_DLAB 0x80 |
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63 #define NS16550_LCR_BREAK 0x40 |
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64 #define NS16550_LCR_STICK 0x20 |
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65 #define NS16550_LCR_EPS 0x10 |
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66 #define NS16550_LCR_PEN 0x08 |
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67 #define NS16550_LCR_STB 0x04 |
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68 #define NS16550_LCR_WLS 0x03 |
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69 #define NS16550_LCR_WLS_5 0x00 |
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70 #define NS16550_LCR_WLS_6 0x01 |
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71 #define NS16550_LCR_WLS_7 0x02 |
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72 #define NS16550_LCR_WLS_8 0x03 |
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73 |
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74 /* MCR bits */ |
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75 #define NS16550_MCR_LOOP 0x10 |
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76 #define NS16550_MCR_OUT2 0x08 |
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77 #define NS16550_MCR_OUT1 0x04 |
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78 #define NS16550_MCR_RTS 0x02 |
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79 #define NS16550_MCR_DTR 0x01 |
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80 |
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81 /* LSR bits */ |
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82 #define NS16550_LSR_ERR 0x80 |
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83 #define NS16550_LSR_TEMP 0x40 |
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84 #define NS16550_LSR_THRE 0x20 |
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85 #define NS16550_LSR_BI 0x10 |
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86 #define NS16550_LSR_FE 0x08 |
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87 #define NS16550_LSR_PE 0x04 |
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88 #define NS16550_LSR_OE 0x02 |
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89 #define NS16550_LSR_DR 0x01 |
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90 |
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91 /* MSR bits */ |
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92 #define NS16550_MSR_DCD 0x80 |
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93 #define NS16550_MSR_RI 0x40 |
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94 #define NS16550_MSR_DSR 0x20 |
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95 #define NS16550_MSR_CTS 0x10 |
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96 #define NS16550_MSR_DDCD 0x08 |
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97 #define NS16550_MSR_TERI 0x04 |
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98 #define NS16550_MSR_DDSR 0x02 |
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99 #define NS16550_MSR_DCTS 0x01 |
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100 |
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101 #endif /* __NS16550_H */ |