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annotate gsm-fw/services/ffs/intelsbdrv.c @ 939:62ca61292b77

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gsm-fw: Intel single bank flash driver (Compal) compiles and links
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 31 Oct 2015 23:21:40 +0000
parents 1db4da08b9b4
children 51f580665110
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938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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1 /******************************************************************************
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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2 * Flash File System (ffs)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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4 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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5 * FFS AMD single bank low level flash driver RAM code
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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6 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
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8 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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9 ******************************************************************************/
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10
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11 #include "../../include/config.h"
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12 #include "ffs.h"
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13 #include "drv.h"
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14 #include "ffstrace.h"
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15 #include "intctl.h"
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16
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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17
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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18 #undef tlw
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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19 #define tlw(contents)
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20 #undef ttw
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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21 #define ttw(contents)
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22
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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23 // Status bits for Intel flash memory devices
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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24 #define INTEL_STATE_MACHINE_DONE (1<<7)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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25 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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26 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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27
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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28 /******************************************************************************
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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29 * INTEL Single Bank Driver Functions
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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30 ******************************************************************************/
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31 // Actually we should have disabled and enable the interrupts in this
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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32 // function, but when the interrupt functions are used Target don't run!
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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33 // Anyway, currently the interrupts are already disabled at this point thus
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34 // it does not cause any problems.
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35 int ffsdrv_ram_intel_sb_init(void)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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36 {
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37 uint32 i;
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38 volatile uint16 *addr;
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39
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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40 for (i = 0; i < dev.numblocks; i++)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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41 {
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42 addr = (volatile uint16 *) block2addr(i);
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43
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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44 *addr = 0x60; // Intel Config Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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45 *addr = 0xD0; // Intel Unlock Block
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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46
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47 *addr = 0xFF; // Intel Read Array
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48 }
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49
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50 return 0;
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51 }
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52
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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53 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
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54 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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55 uint32 cpsr;
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56
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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57 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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58
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59 if (~*addr & value) {
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60 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
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61 return;
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62 }
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63
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64 cpsr = int_disable();
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65 tlw(led_on(LED_WRITE));
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66
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67 #if (INTEL_UNLOCK_SLOW == 1)
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68 *addr = 0x60; // Intel Config Setup
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69 *addr = 0xD0; // Intel Unlock Block
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70 #endif
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71
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72 *addr = 0x50; // Intel Clear Status Register
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73 *addr = 0x40; // Intel program byte/word
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74 *addr = value;
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75 while ((*addr & 0x80) == 0)
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76 ;
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77 *addr = 0xFF; // Intel read array
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Mychaela Falconia <falcon@ivan.Harhan.ORG>
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78 tlw(led_off(LED_WRITE));
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79 int_enable(cpsr);
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80 }
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81
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82 void ffsdrv_ram_intel_sb_erase(uint8 block)
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83 {
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84 volatile uint16 *addr;
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85 uint32 cpsr;
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86 uint16 poll;
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87
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88 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
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89
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90 addr = (volatile uint16 *) block2addr(block);
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91
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92 cpsr = int_disable();
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93 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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94
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95 #if (INTEL_UNLOCK_SLOW == 1)
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96 *addr = 0x60; // Intel Config Setup
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97 *addr = 0xD0; // Intel Unlock Block
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98 #endif
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99
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100 *addr = 0x50; // Intel Clear Status Register
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Mychaela Falconia <falcon@ivan.Harhan.ORG>
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101 *addr = 0x20; // Intel Erase Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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102 *addr = 0xD0; // Intel Erase Confirm
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103 *addr = 0x70; // Intel Read Status Register
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104
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105 // Wait for erase to finish.
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106 while ((*addr & 0x80) == 0) {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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107 tlw(led_toggle(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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108 // Poll interrupts, taking interrupt mask into account.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
109 if (INT_REQUESTED)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
110 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
111 // 1. suspend erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
112 // 2. enable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
113 // .. now the interrupt code executes
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
114 // 3. disable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
115 // 4. resume erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
116
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
117 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
118
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
119 *addr = 0xB0; // Intel Erase Suspend
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
120 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
121 while (((poll = *addr) & 0x80) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
122 ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
123
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
124 // If erase is complete, exit immediately
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
125 if ((poll & 0x40) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
126 break;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
127
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
128 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
129
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
130 tlw(led_off(LED_ERASE_SUSPEND));
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
131 int_enable(cpsr);
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
132
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
133 // Other interrupts and tasks run now...
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
134
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
135 cpsr = int_disable();
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
136 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
137
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
138 *addr = 0xD0; // Intel erase resume
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
139 // The following "extra" Read Status command is required because Intel has
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
140 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
141 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
142 // Specification Update")
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
143 *addr = 0x70; // Intel Read Status Register
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
144
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
145 tlw(led_off(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
146 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
147 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
148 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
149
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
150 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
151 tlw(led_off(LED_ERASE));
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
152 int_enable(cpsr);
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
153 }