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annotate gsm-fw/cfgmagic/target.pirelli @ 937:631fb20ff8d4

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gsm-fw/cfgmagic: beginning of support for Intel single bank flash (Compal) in addition to the currently supported AMD multibank (Openmoko and Pirelli)
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 31 Oct 2015 21:50:43 +0000
parents 452a4aea3fc5
children 042c178ebac5
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ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 CONFIG_TARGET_PIRELLI=1
ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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2 export_to_c CONFIG_TARGET_PIRELLI
890
452a4aea3fc5 gsm-fw: implemented reading of Pirelli's factory calibration records
Space Falcon <falcon@ivan.Harhan.ORG>
parents: 522
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3 export_to_mk CONFIG_TARGET_PIRELLI
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ccde45a06737 nuc-fw: beginning of the configuration mechanism
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ccde45a06737 nuc-fw: beginning of the configuration mechanism
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5 CONFIG_IRAM_SIZE=0x80000
ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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6 CONFIG_XRAM_SIZE=0x800000
ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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7 CONFIG_FWFLASH_SIZE=0x800000
ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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8 # the post-target fragment exports these
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c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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10 # RAMFFS: default to 64 KiB x 8
c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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11 RAMFFS_BLKSIZE_LOG2=16
c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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12 RAMFFS_NBLOCKS=8
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parents: 143
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13
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631fb20ff8d4 gsm-fw/cfgmagic: beginning of support for Intel single bank flash (Compal)
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 890
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14 # select the correct flash driver
631fb20ff8d4 gsm-fw/cfgmagic: beginning of support for Intel single bank flash (Compal)
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 890
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15 Flash_type=AMD-multibank
631fb20ff8d4 gsm-fw/cfgmagic: beginning of support for Intel single bank flash (Compal)
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 890
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c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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17 # 2nd flash chip select
c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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18 FLASH2_BASE_ADDR=0x02000000
c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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19 export_to_c FLASH2_BASE_ADDR
c70c077243dd gsm-fw: beginning of config magic for FFS
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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21 DBB_type=751992A
ccde45a06737 nuc-fw: beginning of the configuration mechanism
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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22 ABB_type=Iota3014
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3b2e941043d8 nuc-fw/bsp: niq32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 88
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23 RF_type=Rita
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ccde45a06737 nuc-fw: beginning of the configuration mechanism
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24 # the post-target fragment will turn these into TI's voodoo numbers
522
2c9c2b95ddec FC version of l1_rf12.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 512
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25
2c9c2b95ddec FC version of l1_rf12.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 512
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26 # For the RF PA we have to set TI's voodoo number directly, and we don't
2c9c2b95ddec FC version of l1_rf12.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 512
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27 # even have a number for these Skyworks parts. :-(
2c9c2b95ddec FC version of l1_rf12.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 512
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28 # The best we can do for now is lie and pretend to be Leonardo/Openmoko.
2c9c2b95ddec FC version of l1_rf12.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 512
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29 RF_PA=2