FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/sysglue/flashboot.S @ 635:658a83ff7221
gsm-fw/sysglue/flashboot.S: buglet in the previous change
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Mon, 01 Sep 2014 18:45:37 +0000 |
parents | 1f54d2ba42c2 |
children | 06ecb305f650 |
rev | line source |
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gsm-fw/sysglue: prep for building flashable images
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1 /* |
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2 * This assembly module contains those bits which are specific to flashable |
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3 * image builds only. It puts bits of code into several different sections. |
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4 */ |
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5 |
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6 #include "../include/config.h" |
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7 |
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8 .section flashboot.text,"ax",%progbits |
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9 .code 32 |
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10 .org 0 |
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11 #if FLASH_BOOT_VIA_BOOTROM |
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12 /* sane targets with Calypso boot ROM enabled by the PCB wiring */ |
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13 /* provide the necessary magic words for the boot ROM */ |
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14 .word 0 |
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15 .word _Flash_boot_entry |
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16 #elif CONFIG_TARGET_C139 |
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17 /* |
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18 * On this target we are going to put a special flash boot stage at 0x2000, |
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19 * and then the actual gsm-fw image at the flash erase block boundary |
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20 * at 0x10000. The following bits will be read by our intermediate |
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21 * flash boot stage. |
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22 */ |
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23 .asciz "FreeCalypso" |
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24 .word _Flash_boot_entry |
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25 #elif CONFIG_TARGET_C155 |
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26 /* |
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27 * On this target the hand-off point between the bootloader and the main |
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28 * fw image coincides with a flash erase block boundary, thus no need |
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29 * for an intermediate flash boot stage. The following bits will appear |
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30 * at 0x20000. |
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31 */ |
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32 .asciz "FreeCalypso firmware for C155/156 target" |
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33 .org 0xE0 |
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34 /* C155/156 bootloader jumps here */ |
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35 b _Flash_boot_entry |
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36 #include "vectors.S" |
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37 #else |
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38 #error "Unsupported flash boot configuration" |
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39 #endif |
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40 |
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41 .globl _Flash_boot_entry |
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42 _Flash_boot_entry: |
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43 /* first order of business: configure flash and XRAM access */ |
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44 ldr r2, =0xFFFFFB00 |
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45 #if CONFIG_TARGET_PIRELLI |
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46 mov r0, #0x00A4 |
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47 strh r0, [r2, #0] |
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48 strh r0, [r2, #2] |
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49 strh r0, [r2, #6] |
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50 #else |
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51 mov r0, #0x00A3 |
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52 strh r0, [r2, #0] |
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53 strh r0, [r2, #2] |
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54 #endif |
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55 /* |
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56 * On targets with 8 MiB flash (or XRAM) banks we need to switch the |
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57 * CS4/ADD22 pin to the ADD22 function. We could do it for all targets |
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58 * (not aware of any that need the pin to be CS4), but we strongly |
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59 * prefer to have a consistent execution environment between flashImage |
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60 * and ramImage, so let's only do this setting on those targets |
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61 * on which we do it in ../../loadtools/scripts/*.init (for fc-xram). |
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62 */ |
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63 #if CONFIG_TARGET_PIRELLI || CONFIG_TARGET_C155 |
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64 ldr r1, =0xFFFEF006 |
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65 mov r2, #0x0008 |
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66 strh r2, [r1] |
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67 #endif |
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68 /* we now have full access to all flash and RAM on the device */ |
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69 /* copy iram.text to where it's supposed to be */ |
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70 ldr r8, =__iramtext_flash_addr |
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71 ldr r9, =__iramtext_ram_addr |
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72 ldr r10, =__iramtext_size |
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73 1: ldmia r8!, {r0-r7} |
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74 stmia r9!, {r0-r7} |
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75 subs r10, r10, #0x20 |
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76 bhi 1b |
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77 /* likewise copy .data from flash to XRAM */ |
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78 ldr r8, =__initdata_flash_addr |
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79 ldr r9, =__initdata_ram_addr |
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80 ldr r10, =__initdata_size |
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81 1: ldmia r8!, {r0-r7} |
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82 stmia r9!, {r0-r7} |
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83 subs r10, r10, #0x20 |
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84 bhi 1b |
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85 /* boot path joins with fc-xram loadable builds */ |
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86 b _FlashorXram_entry |