FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/services/etm/etm_tmcore.c @ 915:7b805007dcfc
etmsync: slight "main" refactoring in preparation for multiple programs
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Tue, 08 Sep 2015 18:26:42 +0000 |
parents | f9ac53d8e999 |
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rev | line source |
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1 /******************************************************************************** |
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2 * Enhanced TestMode (ETM) |
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3 * @file tmcore.c |
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4 * |
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5 * @author Kim T. Peteren (ktp@ti.com) |
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6 * @version 0.1 |
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7 * |
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8 |
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9 * |
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10 * History: |
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11 * |
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12 * Date Modification |
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13 * ------------------------------------ |
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14 * 16/06/2003 Creation |
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15 * 02/07/2003 Removed l1_config.TestMode check from CODEC Write |
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16 * 17/03/2004 Updated etm_version |
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17 * 30/03/2004 Updated etm_dieID_read() func. regarding get die id for 16 bits |
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18 * instead of 8 bits. |
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19 * |
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20 * (C) Copyright 2003 by Texas Instruments Incorporated, All Rights Reserved |
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21 *********************************************************************************/ |
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22 |
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23 #include "../../riviera/rv/rv_defined_swe.h" |
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24 #include "../../riviera/rv/rv_general.h" |
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25 |
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26 #include "etm.h" |
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27 #include "etm_config.h" |
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28 #include "etm_api.h" |
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29 #include "etm_trace.h" |
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30 #include "etm_version.h" |
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31 |
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32 #include "../../bsp/abb+spi/abb.h" |
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33 #include "../../bsp/abb+spi/spi_drv.h" |
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34 |
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35 extern void tr_etm_init(unsigned int mask); |
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36 |
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37 // Version of the ETM CORE module |
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38 // See the file etm_version.h |
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39 |
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40 /****************************************************************************** |
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41 * DIE ID settings |
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42 *****************************************************************************/ |
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43 |
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44 /* DIE ID register */ |
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45 #if ((CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) //For D-Sample: $CHIPSET = 8 (=10 for D-sample AMR, 11 for GSMLITE). |
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46 #define DIE_ID_REG (MEM_DEV_ID0 | 0xF010) //+ 0xFFFEF010 for Calypso |
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47 #else |
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48 #if (CHIPSET == 12) //For E-Sample: $CHIPSET = 12. |
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49 #define DIE_ID_REG (0xFFFE0000 | 0xF004) //+ 0xFFFEF004 for Calypso Plus |
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50 #endif |
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51 #endif |
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52 |
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53 /* DIE ID SIZE is 4 words (16 bits)long */ |
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54 #define DIE_ID_SIZE 4 |
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55 |
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56 |
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57 /****************************************************************************** |
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58 * Internal prototypes |
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59 *****************************************************************************/ |
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60 |
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61 T_ETM_PKT *etm_core_setup(uint8 fid); |
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62 int etm_core(uint8 *buf, int size); |
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63 |
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64 /****************************************************************************** |
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65 * Register the Core Module to the ETM database |
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66 *****************************************************************************/ |
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67 |
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68 int etm_core_init(void) |
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69 { |
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70 int result; |
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71 |
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72 result = etm_register("CORE", ETM_CORE, 0, 0, etm_core); |
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73 return result; |
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74 } |
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75 |
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76 |
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77 /****************************************************************************** |
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78 * Memory read/write Functions |
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79 *****************************************************************************/ |
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80 |
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81 // Describe the payload of the mem protocol !!!!!! |
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82 // |--type(1)-|--partnum(1)-|--addr(4)-|--data(?)-| |
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83 |
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84 int etm_mem(T_ETM_PKT *pkt, uint8 *buf) |
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85 { |
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86 int num, unitsize, error; |
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87 uint8 type, param; |
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88 uint8 *mem8; |
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89 uint16 *mem16; |
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90 uint32 *mem32; |
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91 uint32 addr, tmp; |
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92 |
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93 param = unitsize = *buf & 0x3; |
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94 if (unitsize == 0) |
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95 unitsize = 4; |
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96 |
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97 type = *buf & 0x10; |
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98 buf++; |
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99 |
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100 num = *buf++; |
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101 addr = etm_get32(buf); |
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102 buf += 4; |
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103 |
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104 tr_etm(TgTrCore, "ETM CORE: _mem: type(0x%x) addr(0x%x) partnum(%d)", type, addr, num); |
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105 |
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106 // Put 'parameter' in return packet |
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107 if ((error = etm_pkt_put8(pkt, param)) < 0) { |
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108 return error; |
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109 } |
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110 |
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111 switch (type) { |
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112 case 0: // READ(0x00) |
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113 switch (unitsize) { |
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114 case 1: |
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115 mem8 = (uint8 *) addr; |
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116 while (num--) { |
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117 if ((error = etm_pkt_put8(pkt, *mem8++)) < 0) |
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118 break; |
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119 } |
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120 break; |
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121 case 2: |
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122 mem16 = (uint16 *) addr; |
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123 while (num--) { |
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124 if ((error = etm_pkt_put16(pkt, *mem16++)) < 0) |
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125 break; |
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126 } |
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127 break; |
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128 case 4: |
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129 mem32 = (uint32 *) addr; |
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130 while (num--) { |
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131 if ((error = etm_pkt_put32(pkt, *mem32++)) < 0) |
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132 break; |
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133 } |
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134 break; |
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135 } |
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136 break; |
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137 |
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138 case 16: // WRITE(0x10) |
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139 switch (unitsize) { |
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140 case 1: |
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141 mem8 = (uint8 *) addr; |
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142 while (num--) { |
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143 *mem8++ = etm_get8(buf); |
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144 buf += 1; |
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145 } |
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146 break; |
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147 case 2: |
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148 mem16 = (uint16 *) addr; |
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149 while (num--) { |
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150 *mem16++ = tmp = etm_get16(buf); |
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151 buf += 2; |
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152 } |
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153 break; |
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154 case 4: |
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155 mem32 = (uint32 *) addr; |
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156 while (num--) { |
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157 *mem32++ = etm_get32(buf); |
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158 buf += 4; |
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159 } |
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160 break; |
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161 } |
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162 break; |
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163 default: |
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164 return ETM_NOSYS; |
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165 } |
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166 |
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167 if (error < 0) |
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168 return error; |
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169 |
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170 return ETM_OK; |
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171 } |
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172 |
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173 |
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174 /****************************************************************************** |
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175 * CODEC Functions |
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176 *****************************************************************************/ |
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177 |
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178 // ETM sends both page value and register address in one byte. |
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179 // Bit field is: PPPR RRRR |
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180 // where P = page bit, R = register address bits and X = don't care bits. |
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181 |
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182 int etm_codec_write(T_ETM_PKT *pkt, uint8 *buf) |
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183 { |
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184 uint16 page, reg, data; |
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185 int result, reg_data; |
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186 |
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187 reg_data = *buf++; |
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188 if ((result = etm_pkt_put8(pkt, reg_data)) < 0) |
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189 return result; |
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190 |
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191 page = (reg_data >> 5) & 0x3; |
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192 reg = reg_data & 0x1F; |
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193 data = etm_get16(buf); |
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194 |
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195 tr_etm(TgTrCore, "ETM CORE: _codec_write: page(%d) reg(%d) data(0x%x)", |
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196 page, reg, (data & 0x3ff)); |
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197 |
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198 if (page > 7 && reg > 32) |
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199 return ETM_INVAL; |
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200 else { |
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201 // The function below expects a 1 for page 0 and a 2 for page 1. |
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202 // The register address value is left-shifted by 1 since LSB is read/write command bit. |
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203 // The value is written in the 10 MSB's of register. |
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204 ABB_Write_Register_on_page(page + 1, reg << 1, (data & 0x3ff)); |
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205 } |
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206 |
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207 return ETM_OK; |
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208 } |
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209 |
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210 |
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211 int etm_codec_read(T_ETM_PKT *pkt, uint8 *buf) |
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212 { |
166
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213 uint16 value; |
164
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214 uint16 page, reg; |
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215 int result, reg_data; |
166
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164
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216 |
164
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217 reg_data = *buf; |
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218 if ((result = etm_pkt_put8(pkt, reg_data)) < 0) |
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219 return result; |
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220 |
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221 page = (reg_data >> 5) & 0x3; |
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222 reg = reg_data & 0x1F; |
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223 |
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224 if (page > 7 && reg > 32) |
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225 return ETM_INVAL; |
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226 |
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227 // The function below expects a 1 for page 0 and a 2 for page 1. |
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228 // The register value is left-shifted by 1 since LSB is read/write command bit. |
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229 value = ABB_Read_Register_on_page(page + 1, (reg << 1)); |
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230 |
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231 tr_etm(TgTrCore, "ETM CORE: _codec_read: page(%d) reg(%d) value(0x%x)", page, reg, value); |
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232 |
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233 result = etm_pkt_put16(pkt, value); |
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234 return result; |
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235 } |
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236 |
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237 |
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238 /****************************************************************************** |
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239 * Echo and Reset Functions |
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240 *****************************************************************************/ |
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241 |
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242 //structur of data dl: |delay|recvsize|num| = 3x2 bytes |
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243 int etm_echo(T_ETM_PKT *pkt, uint8 *data) |
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244 { |
193
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245 int delay, sendsize, i; |
164
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246 |
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247 tr_etm(TgTrCore, "etm_echo:"); |
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248 |
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249 delay = etm_get16(data); |
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250 data += 2; |
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251 |
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252 sendsize = etm_get16(data); |
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253 if (sendsize > 240) |
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254 return ETM_INVAL; |
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255 |
193
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256 tr_etm(TgTrCore, "ETM CORE: _echo: delay(%d) sendsize(%d)", |
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257 delay, sendsize); |
164
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258 |
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259 if (delay > 0) { |
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260 rvf_delay((delay + 32) * 14 / 64); |
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261 } |
193
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262 |
164
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263 for (i = 0; i < sendsize; i++) { |
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264 pkt->data[i+1] = i; // data[0] = fid |
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265 } |
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266 |
193
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267 pkt->size = sendsize + 1; |
164
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268 |
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269 return ETM_OK; |
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270 } |
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271 |
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272 |
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273 int etm_reset(void) |
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274 { |
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275 // The reset code is taken form Fluid->cmd.c |
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276 int i; |
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277 |
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278 tr_etm(TgTrCore, "ETM CORE: _reset: Target is Reset"); |
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279 |
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280 // Setup watchdog timer and let it timeout to make a reset |
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281 *(volatile uint16*) 0xfffff804 = 0xFFFF; // Timer to watchdog |
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282 *(volatile uint16*) 0xfffff800 = 0x0080; // Start timer |
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283 // Apparently works it only if we read this register? |
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284 i = *(volatile uint16*) 0xfffff802; |
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285 *(volatile uint16*) 0xfffff802 = 0x0001; // Load timer |
166
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286 |
164
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287 return ETM_OK; |
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288 } |
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289 |
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290 |
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291 /****************************************************************************** |
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292 * Set Test Controls |
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293 *****************************************************************************/ |
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294 |
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295 int etm_debug(T_ETM_PKT *pkt, uint8 *buf) |
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296 { |
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297 int type, error, data; |
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298 |
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299 static char *p; |
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300 |
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301 type = *buf & 0x0F; |
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302 buf++; |
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303 |
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304 data = etm_get32(buf); |
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305 |
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306 tr_etm(TgTrCore, "ETM CORE: _debug: type(%d) data(0x%x)", type, data); |
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307 |
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308 switch (type) { |
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309 case 0: // (0x00) Allocate Test Buffer |
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310 if ((p = etm_malloc(data)) == NULL) |
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311 error = ETM_NOMEM; |
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312 error = etm_pkt_put32(pkt, (int) p); |
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313 break; |
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314 case 1: // (0x01) Free Test Buffer. |
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315 p = (char *) data; |
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316 etm_free(p); |
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317 break; |
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318 case 2: // (0x02) Set ETM Trace mask |
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319 tr_etm_init(data); |
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320 break; |
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321 case 3: // (0x03) Set read all mem banks stat |
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322 rvf_dump_mem(); |
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323 rvf_dump_pool(); |
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324 rvf_dump_tasks(); |
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325 break; |
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326 default: |
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327 error = ETM_NOSYS; |
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328 } |
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329 |
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330 if (error < 0) |
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331 return error; |
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332 |
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333 return ETM_OK; |
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334 } |
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335 |
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336 /****************************************************************************** |
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337 * Get Version of ... |
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338 *****************************************************************************/ |
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339 // This is in development ... |
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340 |
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341 int etm_version(T_ETM_PKT *pkt, uint8 *buf) |
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342 { |
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343 extern uint16 etm_audio_revision; |
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344 extern uint16 etm_task_revision; |
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345 int error, fid, ffs_tm_version; |
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346 volatile int revision = 0; |
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347 #if 0 |
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348 T_VERSION *l1s_version; |
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349 #endif |
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350 |
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351 fid = etm_get32(buf); |
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352 |
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353 tr_etm(TgTrCore, "ETM CORE: _version: fid(0x%x)", fid); |
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354 |
166
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355 #if 0 |
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356 l1s_version = (T_VERSION*) l1s_get_version(); |
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357 #endif |
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358 |
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359 switch (fid) { |
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360 // Code Versions related to ETM modules |
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361 case SW_REV_ETM_CORE: |
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362 error = etm_pkt_put32(pkt, ETM_CORE_VERSION); |
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363 break; |
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364 case SW_REV_ETM_AUDIO: |
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365 error = etm_pkt_put32(pkt, ETM_AUDIO_VERSION); |
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366 break; |
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367 // case SW_REV_ETM_FFS: |
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368 // ffs_query(Q_FFS_TM_VERSION, &ffs_tm_version); |
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369 // error = etm_pkt_put32(pkt, ffs_tm_version); |
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370 break; |
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371 // case SW_REV_ETM_RF: // Layer1 Testmode Version |
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372 // error = etm_pkt_put32(pkt, TESTMODEVERSION); |
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373 // break; |
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374 case SW_REV_ETM_PWR: |
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375 error = etm_pkt_put32(pkt, ETM_PWR_VERSION); |
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376 break; |
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377 case SW_REV_ETM_BT: |
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378 error = ETM_NOSYS; |
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379 break; |
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380 case SW_REV_ETM_TASK: |
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381 error = etm_pkt_put32(pkt, ETM_VERSION); |
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382 break; |
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383 case SW_REV_ETM_API: |
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384 error = etm_pkt_put32(pkt, ETM_API_VERSION); |
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385 break; |
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386 // Code Versions related to L1, see in l1_defty.h |
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387 // Get the version on this way "revision = l1s.version.dsp_code_version;" |
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388 // doesn't work because of struct aligment -> compile flag -mw !!!! |
166
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389 #if 0 |
164
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390 case SW_DSP_CODE_VERSION: |
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391 revision = ((T_VERSION*) l1s_version)->dsp_code_version; |
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392 error = etm_pkt_put32(pkt, revision); |
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393 break; |
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394 case SW_DSP_PATCH_VERSION: |
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395 revision = ((T_VERSION*) l1s_version)->dsp_patch_version; |
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396 error = etm_pkt_put32(pkt, revision); |
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397 break; |
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398 case SW_MCU_TCS_PROGRAM_RELEASE: |
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399 revision = ((T_VERSION*) l1s_version)->mcu_tcs_program_release; |
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400 error = etm_pkt_put32(pkt, revision); |
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401 break; |
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402 case SW_MCU_TCS_OFFICIAL: // This version allso identify version of Layer1 |
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403 revision = ((T_VERSION*) l1s_version)->mcu_tcs_official; |
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404 error = etm_pkt_put32(pkt, revision); |
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405 break; |
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406 case SW_MCU_TCS_INTERNAL: |
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407 revision = ((T_VERSION*) l1s_version)->mcu_tcs_internal; |
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408 error = etm_pkt_put32(pkt, revision); |
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409 break; |
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410 case SW_MCU_TM_VERSION: |
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411 revision = ((T_VERSION*) l1s_version)->mcu_tm_version; |
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412 error = etm_pkt_put32(pkt, revision); |
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413 break; |
166
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414 #endif |
164
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415 default: |
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416 error = ETM_NOSYS; |
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417 } |
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418 |
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419 tr_etm(TgTrCore, "ETM CORE: _version: version(%d)", revision); |
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420 |
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421 if (error < 0) |
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422 return error; |
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423 |
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424 return ETM_OK; |
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425 } |
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426 |
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427 |
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428 /****************************************************************************** |
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429 * Function for reading the Die-ID from base band processor. |
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430 *****************************************************************************/ |
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431 |
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432 int etm_dieID_read(T_ETM_PKT *pkt, uint8 *inbuf) |
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433 { |
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434 T_RV_RET result; |
193
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435 int8 i; |
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436 UINT16 val; |
164
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437 volatile UINT16 *reg_p = (UINT16 *) DIE_ID_REG; |
193
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438 |
164
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439 tr_etm(TgTrCore, "ETM CORE: _dieID_read: started - Die-ID address(0x%x)", DIE_ID_REG); |
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440 |
193
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441 for (i = 0; i < DIE_ID_SIZE; i++) { |
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442 val = *reg_p++; |
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443 result = etm_pkt_put16(pkt, val); |
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444 if (result < 0) |
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445 return result; |
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446 } |
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447 |
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448 return ETM_OK; |
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449 } |
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450 |
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451 |
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452 /****************************************************************************** |
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453 * ETM CORE Main Function - Module |
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454 *****************************************************************************/ |
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455 |
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456 int etm_core(uint8 *buf, int size) |
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457 { |
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458 // Structur of protocol data dl-link: |fid|index|data| |
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459 |
193
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460 /* |
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461 * As the comments below imply, the opcodes for tmcore commands used |
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462 * to be mnemonic ASCII letters, but then at some point for some |
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463 * non-understood reason TI decided to change them to the current set. |
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464 * |
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465 * I thought about changing back to the old opcodes for FreeCalypso, |
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466 * but given that all of the available existing firmwares (mokoN, the |
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467 * already-released leo2moko-r1, and Pirelli's fw) use the "new" opcodes, |
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468 * I've decided to stick with the same for consistency, and let our |
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469 * fc-tmsh work with both our own fw and the available pre-existing ones. |
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470 */ |
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471 |
164
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472 uint8 mid; |
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473 uint8 fid; |
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474 int error = 0; |
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475 T_ETM_PKT *pkt = NULL; |
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476 |
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477 fid = *buf++; |
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478 |
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479 tr_etm(TgTrCore, "ETM CORE: _core: fid(%c):", fid); |
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480 |
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481 /* Create TestMode return Packet */ |
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482 if ((pkt = (T_ETM_PKT *) etm_malloc(sizeof(T_ETM_PKT))) == NULL) { |
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483 return ETM_NOMEM; |
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484 } |
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485 |
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486 // Init. of return packet |
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487 pkt->mid = ETM_CORE; |
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488 pkt->status = ETM_OK; |
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489 pkt->size = 0; |
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490 pkt->index = 0; |
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491 etm_pkt_put8(pkt, fid); |
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492 |
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493 switch (fid) { |
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494 #if ETM_ATP_SUPPORT |
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495 case 0x60: // old 'G' |
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496 error = etm_at(pkt, (char *) buf); |
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497 break; |
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498 #endif |
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499 case 0x61: // old 'M' |
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500 error = etm_mem(pkt, buf); |
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501 break; |
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502 case 0x62: // old 'E' |
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503 error = etm_echo(pkt, buf); |
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504 break; |
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505 case 0x63: // old 'R' |
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506 error = etm_reset(); |
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507 break; |
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508 case 0x64: // old 'T' |
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509 error = etm_debug(pkt, buf); |
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510 break; |
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511 case 0x65: // old 'V' |
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512 error = etm_version(pkt, buf); |
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513 break; |
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514 case 0x66: // old 'C' |
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515 error = etm_codec_read(pkt, buf); |
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516 break; |
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517 case 0x67: // old 'D' |
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518 error = etm_codec_write(pkt, buf); |
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519 break; |
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520 case 0x68: // old 'd' |
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521 error = etm_dieID_read(pkt, buf); |
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522 break; |
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523 default: |
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524 tr_etm(TgTrCore,"ETM CORE: _core: fid ERROR"); |
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525 error = ETM_NOSYS; |
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526 break; |
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527 } |
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528 |
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529 if (error < 0) { |
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530 tr_etm(TgTrCore,"ETM CORE: _core: FAILED"); |
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531 pkt->status = -error; |
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532 } |
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533 |
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534 // etm_at(): send func. is controlled by primitive |
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535 if (fid == 'G' && error >= RV_OK) {} |
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536 else |
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537 etm_pkt_send(pkt); |
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538 |
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539 etm_free(pkt); |
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540 return ETM_OK; |
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541 } |