FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/armio.c @ 326:7e878e6b9cf7
gsm-fw/gpf/tst_drv: tif2.c compiles
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sat, 19 Apr 2014 05:23:11 +0000 |
parents | afceeeb2cba1 |
children | 383abdbc5d35 |
rev | line source |
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1 /* |
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2 * ARMIO.C |
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3 * |
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4 * |
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5 * Control diagnostic bits |
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6 * |
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7 * Reference : GCS207 |
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8 * |
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9 */ |
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10 |
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11 |
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12 #include "../include/config.h" |
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13 #include "../include/sys_types.h" |
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14 |
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15 #include "mem.h" |
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16 #include "iq.h" |
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17 #include "armio.h" |
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18 |
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19 #if 0 |
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20 /* FreeCalypso: abb.h hasn't been integrated yet */ |
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21 #include "abb.h" // for AI_Power function : to be removed, use ABB_Power_Off in abb.c file instead !!! |
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22 #endif |
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23 |
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24 #if (CHIPSET != 12) |
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25 /* |
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26 * AI_EnableBit |
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27 * |
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28 * Enable ARMIO input/output bit (see CLKM module specification) |
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29 */ |
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30 void AI_EnableBit(int bit) |
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31 { |
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32 *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) |= (1<<bit); |
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33 } |
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34 |
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35 /* |
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36 * AI_DisableBit |
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37 * |
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38 * Disable ARMIO input/output bit (see CLKM module specification) |
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39 */ |
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40 void AI_DisableBit(int bit) |
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41 { |
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42 *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) &= ~(1<<bit); |
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43 } |
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44 |
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45 #endif /* CHIPSET != 12 */ |
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46 |
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47 /* |
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48 * AI_SetBit |
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49 * |
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50 * Switch-on one bit |
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51 */ |
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52 void AI_SetBit(int bit) |
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53 { |
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54 *((volatile SYS_UWORD16 *) ARMIO_OUT) |= (1<<bit); |
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55 } |
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56 |
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57 /* |
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58 * AI_ResetBit |
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59 * |
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60 * Switch-off one bit |
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61 */ |
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62 void AI_ResetBit(int bit) |
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63 { |
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64 *((volatile SYS_UWORD16 *) ARMIO_OUT) &= ~(1<<bit); |
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65 } |
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66 |
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67 /* |
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68 * AI_ConfigBitAsOutput |
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69 * |
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70 * Set this bit as an output |
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71 */ |
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72 void AI_ConfigBitAsOutput(int bit) |
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73 { |
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74 *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) &= ~(1<<bit); |
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75 } |
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76 |
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77 /* |
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78 * AI_ConfigBitAsInput |
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79 * |
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80 * Set this bit as an input |
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81 */ |
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82 void AI_ConfigBitAsInput(int bit) |
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83 { |
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84 *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) |= (1<<bit); |
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85 } |
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86 |
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87 |
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88 /* |
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89 * AI_ReadBit |
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90 * |
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91 * Read value in register |
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92 */ |
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93 SYS_BOOL AI_ReadBit(int bit) |
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94 { |
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95 if ((*((volatile SYS_UWORD16 *) ARMIO_IN)) & (1<<bit)) |
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96 return (1); |
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97 else |
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98 return (0); |
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99 } |
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100 |
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101 /* |
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102 * AI_Power |
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103 * |
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104 * Switch-on or off the board |
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105 * |
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106 * Parameters : SYS_UWORD8 power: 1 to power-on (maintain power) |
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107 * 0 to power-off |
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108 * |
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109 */ |
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110 // #if (!OP_L1_STANDALONE) |
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111 #if 0 |
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112 void AI_Power(SYS_UWORD8 power) |
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113 { |
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114 if (power == 0) |
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115 { |
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116 ABB_Power_Off(); |
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117 } |
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118 } |
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119 #endif |
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120 |
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121 /* |
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122 * AI_ResetIoConfig |
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123 * |
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124 * Reset all default IO configurations |
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125 * |
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126 */ |
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127 void AI_ResetIoConfig(void) |
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128 { |
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129 *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) = 0xFFFF; // all bits are inputs |
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130 #if (CHIPSET != 12) |
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131 *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) = 0; // default config |
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132 #endif /* CHIPSET != 12 */ |
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133 } |
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134 |
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135 |
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136 /* |
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137 * AI_ClockEnable |
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138 * |
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139 * Enable ARMIO clock module |
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140 * |
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141 */ |
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142 void AI_ClockEnable(void) |
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143 { |
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144 *((volatile SYS_UWORD16 *) ARMIO_CNTL_REG) |= ARMIO_CLOCKEN; // set to 1 bit 5 |
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145 } |
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146 |
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147 /* |
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148 * The AI_InitIOConfig() function is target-specific. |
93
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149 */ |
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150 |
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151 #ifdef CONFIG_TARGET_GTAMODEM |
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152 /* version for the Openmoko GTA0x GSM modem */ |
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153 void AI_InitIOConfig(void) |
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154 { |
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155 // reset the IOs config |
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156 AI_ResetIoConfig(); |
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157 |
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158 /* |
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159 * The GTA0x Calypso block is a stripped-down version of the Leonardo, |
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160 * reduced to the absolute minimum that is needed for a slave modem. |
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161 * Almost all of the unused interface pins are left unconnected, only |
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162 * a few are pulled externally to GND or VIO. |
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163 * |
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164 * We handle the unused pins the way TI's code does: configure them |
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165 * as GPIOs, then as outputs driving a fixed value (high for GPIOs 8+, |
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166 * low for 0-7). |
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167 */ |
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168 |
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169 /* I'll be brave and turn the unused TSPDI input into a GPIO4 output */ |
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170 AI_EnableBit(0); |
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171 /* Don't want to do that for the IO5 pin though, as it's wired to SIM_IO |
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172 * through a resistor like on the Leonardo. */ |
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173 AI_DisableBit(1); |
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174 /* |
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175 * The following 2 lines are straight from the Leonardo source: enable |
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176 * GPIO6 and GPIO8. GPIO6 takes the place of an ancient VEGA3(?) compat |
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177 * pin, and GPIO8 takes the place of MCUEN1 which no Leonardo-based |
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178 * design seems to use. |
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179 * |
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180 * Note that GPIO7 is not enabled in this version, so that pin retains |
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181 * its meaning as nRESET_OUT - but it's an unused output, rather than |
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182 * a floating input, so we are fine. |
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183 */ |
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184 AI_EnableBit(2); |
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185 AI_EnableBit(4); |
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186 |
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187 /* |
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188 * The GTA0x modem has no Calypso-interfaced Bluetooth, nor any other |
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189 * use for MCSI, aka the DSP backdoor interface. So we turn these 4 pins |
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190 * into GPIOs driving high output state like TI's code does in the |
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191 * sans-BT configuration. |
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192 */ |
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193 AI_EnableBit(5); |
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194 AI_EnableBit(6); |
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195 AI_EnableBit(7); |
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196 AI_EnableBit(8); |
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197 |
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198 /* ditto for MCUEN2 turned GPIO 13 */ |
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199 AI_EnableBit(9); |
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200 |
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201 // ARMIO_OUT register configuration : |
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202 // set IOs 8,9,10,11,12 and 13 as high |
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203 // set IOs 0 to 7 as low |
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204 // Falcon's note: the BP->AP interrupt line gets set low as desired |
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205 *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F00; |
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206 |
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207 // ARMIO_CNTL_REG register configuration : |
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208 // set IOs 0,1,6,8,9,10,11,12 and 13 as outputs. |
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209 // Falcon's addition: set 2, 3 and 4 as outputs too, |
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210 // as they are no-connects on the board. |
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211 |
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212 AI_ConfigBitAsOutput(0); |
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213 AI_ConfigBitAsOutput(1); |
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214 AI_ConfigBitAsOutput(2); |
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215 AI_ConfigBitAsOutput(3); |
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216 AI_ConfigBitAsOutput(4); |
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217 AI_ConfigBitAsOutput(6); |
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218 AI_ConfigBitAsOutput(8); |
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219 AI_ConfigBitAsOutput(9); |
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220 AI_ConfigBitAsOutput(10); |
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221 AI_ConfigBitAsOutput(11); |
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222 AI_ConfigBitAsOutput(12); |
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223 AI_ConfigBitAsOutput(13); |
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224 } |
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225 #endif |
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226 |
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227 #ifdef CONFIG_TARGET_PIRELLI |
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228 /* version for Pirelli DP-L10 */ |
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229 void AI_InitIOConfig(void) |
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230 { |
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231 // reset the IOs config |
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232 AI_ResetIoConfig(); |
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233 |
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234 /* |
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235 * In the case of the Pirelli, our understanding of the hardware |
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236 * is severely crippled by the lack of schematics and the difficulty of |
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237 * reverse engineering from steve-m's PCB layer grind-down scans. |
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238 * |
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239 * The folllowing ARMIO configuration has been copied from OsmocomBB. |
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240 */ |
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241 AI_EnableBit(0); |
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242 AI_EnableBit(1); |
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243 AI_EnableBit(2); |
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244 AI_EnableBit(3); |
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245 AI_EnableBit(4); |
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246 AI_EnableBit(9); |
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247 /* GPIO out all zeros */ |
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248 *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x0000; |
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249 /* setup outputs like OsmocomBB does */ |
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250 AI_ConfigBitAsOutput(1); |
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251 AI_ConfigBitAsOutput(4); |
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252 AI_ConfigBitAsOutput(7); |
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253 } |
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254 #endif |
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255 |
93
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256 /* |
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257 * AI_SelectIOForIT |
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258 * |
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259 * Select which IO will be used to generate an interrupt. |
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260 * 'Edge' specifies if interrup must be detected on falling or rising edge. |
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261 * |
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262 * Warning: parameters are not checked. |
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263 */ |
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264 |
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265 void AI_SelectIOForIT (SYS_UWORD16 Pin, SYS_UWORD16 Edge) |
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266 { |
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267 #if (CHIPSET == 12) |
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268 /* |
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269 * Update INTERRUPT_LEVEL_REG with Edge configuration on Pin selection |
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270 */ |
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271 GPIO_INTERRUPT_LEVEL_REG = (Edge & 0x0001) << Pin; |
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272 |
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273 /* |
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274 * Update INTERRUPT_MASK_REG to enable interrupt generation on Pin selection |
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275 */ |
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276 GPIO_INTERRUPT_MASK_REG = 1 << Pin; |
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277 #else |
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278 /* |
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279 * Bit SET_GPIO_EVENT_MODE (bit 0) is set to enable the GPIO event mode. |
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280 */ |
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281 |
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282 *((volatile SYS_UWORD16 *) ARMIO_GPIO_EVENT_MODE) = (Pin << 1) + (Edge << 5) + 1; |
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283 #endif |
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284 } |
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285 |
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286 #if (CHIPSET != 12) |
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287 /* |
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288 * AI_CheckITSource |
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289 * |
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290 * Check if the interrupt specified by 'Source' is active or not. |
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291 * |
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292 * Output: 0: IT is not active |
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293 * 1: IT is active |
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294 * |
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295 * Warning: parameters are not checked. |
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296 * |
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297 * Warning: If the keypad and GPIO interrupts may occur the GPIO interrupt |
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298 * must be checked first because the GPIO status bit is reset when |
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299 * the register is read. |
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300 */ |
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301 |
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302 int AI_CheckITSource (SYS_UWORD16 Source) |
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303 { |
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304 return (*((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_INT) & Source ? 1 : 0); |
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305 } |
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306 |
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307 /* |
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308 * AI_UnmaskIT |
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309 * |
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310 * Unmask the IT specified by 'Source' (keyboard or GPIO). |
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311 * |
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312 * Warning: parameters are not checked. |
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313 */ |
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314 |
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315 void AI_UnmaskIT (SYS_UWORD16 Source) |
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316 { |
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317 *((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_MASKIT) &= ~Source; |
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318 } |
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319 |
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320 /* |
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321 * AI_MaskIT |
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322 * |
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323 * Mask the IT specified by 'Source' (keyboard or GPIO). |
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324 * |
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325 * Warning: parameters are not checked. |
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326 */ |
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327 |
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328 void AI_MaskIT (SYS_UWORD16 Source) |
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329 { |
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330 *((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_MASKIT) |= Source; |
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331 } |
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332 #endif /* CHIPSET != 12 */ |
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333 |
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334 #if (CHIPSET == 12) |
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335 |
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336 void AI_MaskIT(SYS_UWORD16 d_io_number) { |
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337 GPIO_INTERRUPT_MASK_REG |= (1 << d_io_number); |
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338 } /* f_gpio_mask_it() */ |
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339 |
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340 void AI_UnmaskIT(SYS_UWORD16 d_io_number) { |
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341 GPIO_INTERRUPT_MASK_REG &= ~(1 << d_io_number); |
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342 } /* f_gpio_unmask_it() */ |
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343 |
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344 #endif |