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annotate gsm-fw/L1/tpudrv/tpudrv12.h @ 753:7f68d2ab0d33

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SIM_TOOLKIT re-enabled: the SIM entity code is broken without it
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 11 Oct 2014 21:24:24 +0000
parents 47754cdb6248
children 7f305eb3c530
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1 /****************** Revision Controle System Header ***********************
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2 * GSM Layer 1 software
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3 * Copyright (c) Texas Instruments 1998
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4 *
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5 * Filename tpudrv12.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ****************** Revision Controle System Header ***********************/
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9
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10 //--- Configuration values
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11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
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12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
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13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
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14 // TeST - Enable Main VCO buffer for test
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15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
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16
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17 #if 0 // FreeCalypso
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18 #include "rf.cfg"
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19 #endif
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20
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21 //--- RITA PG declaration
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22
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23 #define R_PG_10 0
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24 #define R_PG_13 1
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25 #define R_PG_20 2 // For RFPG 2.2, use 2.0
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26 #define R_PG_23 3
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27
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28 //--- PA declaration
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29 #define PA_MGF9009 0
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30 #define PA_RF3146 1
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31 #define PA_RF3133 2
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32 #define PA_PF08123B 3
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33 #define PA_AWT6108 4
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34
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35 #if (RF_PA == PA_MGF9009 || RF_PA == PA_PF08123B)
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36 #define PA_CTRL_INT 0
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37 #else
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38 #define PA_CTRL_INT 1
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39 #endif
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40
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41 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
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42 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
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43 // This is also used in l1_rf12.h to select the SWAP_IQ
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44 #if (RF_PG >= R_PG_20)
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45 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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46 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
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47 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
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48 #elif (RF_PG == R_PG_13)
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49 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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50 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
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51 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
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52 #else
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53 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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54 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
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55 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
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56 #endif
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57
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58 //- Bit definitions for TST register programings, etc
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59 #define BIT_0 0x000001
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60 #define BIT_1 0x000002
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61 #define BIT_2 0x000004
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62 #define BIT_3 0x000008
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63 #define BIT_4 0x000010
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64 #define BIT_5 0x000020
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65 #define BIT_6 0x000040
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66 #define BIT_7 0x000080
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67 #define BIT_8 0x000100
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68 #define BIT_9 0x000200
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69 #define BIT_10 0x000400
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70 #define BIT_11 0x000800
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71 #define BIT_12 0x001000
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72 #define BIT_13 0x002000
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73 #define BIT_14 0x004000
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74 #define BIT_15 0x008000
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75 #define BIT_16 0x010000
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76 #define BIT_17 0x020000
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77 #define BIT_18 0x040000
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78 #define BIT_19 0x080000
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79 #define BIT_20 0x100000
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80 #define BIT_21 0x200000
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81 #define BIT_22 0x400000
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82 #define BIT_23 0x800000
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83
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84 //--- TRF6151 definitions ------------------------------------------
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85
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86 //- BASE REGISTER definitions
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87 #define REG_RX 0x000000 // MODE0
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88 #define REG_PLL 0x000001 // MODE1
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89 #define REG_PWR 0x000002 // MODE2
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90 #define REG_CFG 0x000003 // MODE3
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91
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92 //- TeST REGISTER definitions => Used for WA only
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93 // TeST - PLL2 WA => Define PLL2 TEST register
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94 #define TST_PLL2 0x00001E // MODE 14
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95
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96 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
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97 #define TST_VCO3 0x00000F // MODE 15 (0*16+15*1)
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98 #define TST_VCO4 0x000024 // MODE 36 (2*16+4*1)
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99
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100 // Alpha RF7 WA TeST registers
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101 #define TST_LDO 0x000027 // MODE 39 (2*16+7*1)
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102 #define TST_PLL1 0x00001D // MODE 29 (1*16+13*1)
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103 #define TST_TX2 0x000037 // MODE 55 (3*16+7*1)
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104
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105 // More Alpha RF7 WA TeST registers
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106 #define TST_TX3 0x00003C // MODE 61 (3*16+12*1)
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107 #define TST_TX4 0x00003D // MODE 61 (3*16+13*1)
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108
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109 // PG 2.1 WA TeST registers
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110 #define TST_PLL3 0x00001F // MODE 31 (1*16+15*1)
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111 // #define TST_PLL4 0x00002C // MODE 44 (2*16+12*1)
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112 #define TST_MISC 0x00003E // MODE 62 (3*16+14*1) => Used for setting the VCXO current
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113 #define TST_LO 0x00001C // MODE 28 (1*16+12*1)
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114
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115 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
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116 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
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117 // when accessed, triggers the copy of the serial registers.
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118 // This is necessary to switch into "manual operation mode"
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119 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
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120 #define TX_LOOP_MANUAL BIT_3
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121
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122
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123 //- REG_RX - MODE0
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124 #define BLOCK_DETECT_0 BIT_3
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125 #define BLOCK_DETECT_1 BIT_4
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126 #define RST_BLOCK_DETECT_0 BIT_5
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127 #define RST_BLOCK_DETECT_1 BIT_6
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128 #define READ_EN BIT_7
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129 #define RX_CAL_MODE BIT_8
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130 #define RF_GAIN (BIT_10 | BIT_9)
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131
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132
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133 //- REG_PLL - MODE1
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134 //PLL_REGB
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135 //PLL_REGA
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136
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137 //- REG_PWR - MODE2
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138 #define BANDGAP_MODE_OFF 0x0
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139 #define BANDGAP_MODE_ON_ENA BIT_4
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140 #define BANDGAP_MODE_ON_DIS (BIT_4 | BIT_3)
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141 #define REGUL_MODE_ON BIT_5
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142 // BIT[8..6] band
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143 #define BAND_SELECT_GSM BIT_6
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144 #define BAND_SELECT_DCS BIT_7
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145 #define BAND_SELECT_850_LO BIT_8
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146 #define BAND_SELECT_850_HI (BIT_8 | BIT_6)
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147 #define BAND_SELECT_PCS (BIT_8 | BIT_7)
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148
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149 #define SYNTHE_MODE_OFF 0x0
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150 #define SYNTHE_MODE_RX BIT_9
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151 #define SYNTHE_MODE_TX BIT_10
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152 #define RX_MODE_OFF 0x0
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153 #define RX_MODE_A BIT_11
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154 #define RX_MODE_B1 BIT_12
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155 #define RX_MODE_B2 (BIT_12 | BIT_11)
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156 #define TX_MODE_OFF 0x0
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157 #define TX_MODE_ON BIT_13
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158 #define PACTRL_APC_OFF 0x0
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159 #define PACTRL_APC_ON BIT_14
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160 #define PACTRL_APC_DIS 0x0
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161 #define PACTRL_APC_ENA BIT_15
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162
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163
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164 //- REG_CFG - MODE3
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165 // Common PA controller settings:
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166 #define PACTRL_TYPE_PWR 0x0
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167 #define PACTRL_TYPE_CUR BIT_3
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168 #define PACTRL_IDIOD_30_UA 0x0
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169 #define PACTRL_IDIOD_300_UA BIT_4
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170
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171 // PA controller Clara-like (Power Sensing) settings:
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172 #define PACTRL_VHOME_610_MV (BIT_7 | BIT_5)
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173 #define PACTRL_VHOME_839_MV (BIT_7 | BIT_5)
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174 #define PACTRL_VHOME_1000_MV (BIT_6 | BIT_9)
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175 #define PACTRL_VHOME_1600_MV (BIT_8 | BIT_5)
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176 #define PACTRL_RES_OPEN 0x0
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177 #define PACTRL_RES_150_K BIT_10
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178 #define PACTRL_RES_300_K BIT_11
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179 #define PACTRL_RES_NU (BIT_10 | BIT_11)
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180 #define PACTRL_CAP_0_PF 0x0
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181 #define PACTRL_CAP_12_5_PF BIT_12
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182 #define PACTRL_CAP_25_PF (BIT_13 | BIT_12)
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183 #define PACTRL_CAP_50_PF BIT_13
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184
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185 // PACTRL_CFG contains the configuration of the PACTRL that will
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186 // be put into the REG_CFG register at initialization time
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187 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
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188 // in this #define!!!
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189 #if (RF_PA == 0) // MGF9009 (LCPA)
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190 #define PACTRL_CFG \
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191 PACTRL_IDIOD_300_UA | \
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192 PACTRL_CAP_25_PF | \
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193 PACTRL_VHOME_1000_MV | \
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194 PACTRL_RES_300_K
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195 #elif (RF_PA == 1) // 3146
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196 #define PACTRL_CFG 0
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197
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198 #elif (RF_PA == 2) // 3133
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199 #define PACTRL_CFG 0
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200
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201 #elif (RF_PA == 3) // PF08123B
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202 #define PACTRL_CFG \
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203 PACTRL_TYPE_PWR | \
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204 PACTRL_CAP_50_PF | \
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205 PACTRL_RES_300_K | \
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206 PACTRL_VHOME_610_MV
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207 #elif (RF_PA == 4) // AWT6108
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208 #define PACTRL_CFG 0
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209 #else
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210 #error Unknown PA specifiec!
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211 #endif
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212
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213 // Temperature sensor
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214 #define TEMP_SENSOR_OFF 0x0
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215 #define TEMP_SENSOR_ON BIT_14
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216 // Internal Logic Init Disable
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217 #define ILOGIC_INIT_DIS BIT_15
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218 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
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219 // It was introduced in PG 1.2
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220 // For previous PGs this BIT was unused, so it can be safelly programmed
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221 // for all PGs
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222
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223
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224 // RF signals connected to TSPACT [0..7]
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225 //#define RESET_RF BIT_0 // act0
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226 #define RF_SER_ON BIT_0 // act0
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227 #define RF_SER_OFF 0
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228
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229
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230 #if (FEM_TEST==1)
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231 //for test
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232 #define TEST_TX_ON BIT_2 // act2
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233 #define TEST_RX_ON BIT_3 // act3
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234
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235 //3-band config (D-sample)
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236 #define FEM_1 BIT_1 // act1
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237 #define FEM_2 0 //BIT_2 // act2
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238 #define FEM_3 0 //BIT_3 // act3
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239 #elif (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo
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240 #define TEST_TX_ON 0
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241 #define TEST_RX_ON 0
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242 // 4-band config (E-sample, P2, Leonardo)
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243 #define FEM_7 BIT_2 // act2
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244 #define FEM_8 BIT_1 // act1
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245 #define FEM_9 BIT_4 // act4
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246
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247 #if (RF_PA == 0) // LCPA for ES, P2 and Leo
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248 #define PA_HI_BAND BIT_3 // act3
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249 #define PA_LO_BAND 0
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250 #define PA_OFF 0
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251 #elif (RF_PA == 1) // RF3146 for ES and Leonardo
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252 #define PA_HI_BAND BIT_3 // act3
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253 #define PA_LO_BAND 0
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254 #define PA_OFF 0
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255 #elif (RF_PA == 2) // RF3133 for P2 and Leonardo
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256 #define PA_HI_BAND BIT_3 // act3
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257 #define PA_LO_BAND 0
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258 #define PA_OFF 0
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259 #elif (RF_PA == 4) // AWT6108 for Leonardo
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260 #define PA_HI_BAND BIT_3 // act3
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261 #define PA_LO_BAND 0
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262 #define PA_OFF 0
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263 #else
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264 #error "RF_PA not correctly defined"
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265 #endif
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266
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267 #else // DSample + EVARITA
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268 #if (RF_PA != 3) // Hitachi for EVARITA
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269 #error
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270 #endif
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271
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272 //#define TEST_RX_ON 0
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273 //#define TEST_TX_ON BIT_3 // act3
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274 #define TEST_TX_ON 0
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275 #define TEST_RX_ON BIT_3 // act3
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276
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277 //3-band config (D-sample)
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278 #define FEM_1 BIT_1 // act1
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279 #define FEM_2 BIT_2 // act2
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280 #define FEM_3 BIT_3 // act3
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281 #endif
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282
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283 #if (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo
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284
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285 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9)
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286
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287 #define FEM_OFF ( FEM_PINS ^ 0 )
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288
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289 #define FEM_SLEEP ( 0 )
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290
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291 // This configuration is always inverted.
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292
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293 // 4-band config
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294 // RX_UP/DOWN and TX_UP/DOWN
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295 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
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296 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
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297 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
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298 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
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299
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300 #define RU_850 ( PA_LO_BAND | FEM_PINS ^ 0 )
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301 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
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302 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
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303 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
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304
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305 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
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306 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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307 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
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308 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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309
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310 #define RU_1900 ( PA_LO_BAND | FEM_PINS ^ FEM_8 )
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311 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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312 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
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313 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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314
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315 #else // end BOARD = 43
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316 // start RF HW interfacing with EVARITA
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317
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318 #define FEM_OFF (FEM_1 | FEM_2)
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319 #define FEM_SLEEP (0) // To avoid leakage during Deep-Seep
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320
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321 // 3-band config
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322 // RX_UP/DOWN and TX_UP/DOWN
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323 #define RU_900 ( FEM_1 | FEM_2 )
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324 #define RD_900 ( FEM_1 | FEM_2 )
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325 #define TU_900 ( FEM_1 )
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326 #define TD_900 ( FEM_1 | FEM_2 )
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327
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328 #define RU_850 ( FEM_1 | FEM_2 )
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329 #define RD_850 ( FEM_1 | FEM_2 )
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330 #define TU_850 ( FEM_1 )
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331 #define TD_850 ( FEM_1 | FEM_2 )
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332
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333 #define RU_1800 ( FEM_1 | FEM_2 )
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334 #define RD_1800 ( FEM_1 | FEM_2 )
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335 #define TU_1800 ( FEM_2 )
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336 #define TD_1800 ( FEM_1 | FEM_2 )
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337
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338 #define RU_1900 ( FEM_1 | FEM_2 )
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339 #define RD_1900 ( FEM_1 | FEM_2 )
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340 #define TU_1900 ( FEM_2)
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341 #define TD_1900 ( FEM_1 | FEM_2 )
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342
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343 #endif // BOARD != 43
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344
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345 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
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346 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
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347
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348
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349 //--- TIMINGS ----------------------------------------------------------
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350
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351 /*------------------------------------------*/
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352 /* Download delay values */
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353 /*------------------------------------------*/
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354 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
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355
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356 #define T TPU_CLOCK_RANGE
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357
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358
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359 // - TPU instruction into TSP timings ---
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360 // 1 tpu instruction = 1 qbit
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361 #define DLT_1 1 // 1 tpu instruction = 1 qbit
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362 #define DLT_2 2 // 2 tpu instruction = 2 qbit
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363 #define DLT_3 3 // 3 tpu instruction = 3 qbit
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364 #define DLT_4 4 // 4 tpu instruction = 4 qbit
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365 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
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366
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367 // - Serialization timings ---
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368 // The following values where calculated with Katrin Matthes...
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369 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
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370 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
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371 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
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372 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
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373 // ... while the following values are based on the HYP004.doc document
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374 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
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375 // i.e. 12 / 6 qbit = 2 qbit
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376 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
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377 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
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378
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379 // - TPU command execution + serialization length ---
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380 #define DLT_1B 4 // 3*move + serialization of 7 bits
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381 #define DLT_2B 7 // 4*move + serialization of 2 bytes
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382 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
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383 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
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384
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385
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386 // - INIT (delta or DLT) timings ---
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diff changeset
387 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
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388 #define DLT_I2 8 // Time required to set RF_SER_OFF
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389 #define DLT_I3 5 // Time required to set RF_SER_ON
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390 #define DLT_I4 110 // Regulator Turn-ON time
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391
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392
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diff changeset
393 // - tdt & rdt ---
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394 // MAX GSM (not GPRS) rdt and tdt values are...
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395 //#define rdt 380 // MAX GSM rx delta timing
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diff changeset
396 //#define tdt 400 // MAX GSM tx delta timing
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diff changeset
397 // but current rdt and tdt values are...
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diff changeset
398 #define rdt 0 // rx delta timing
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diff changeset
399 #define tdt 0 // tx delta timing
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diff changeset
400
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diff changeset
401 // - RX timings ---
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diff changeset
402 // - RX down:
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403 // The times below are offsets to when BDLENA goes down
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diff changeset
404 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
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diff changeset
405 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
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diff changeset
406
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diff changeset
407 // - RX up:
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diff changeset
408 // The times below are offsets to when BDLENA goes high
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diff changeset
409 // Burst data comes here
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410 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
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411 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
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412 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
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413 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
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414 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
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415 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
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416 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
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417 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
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418 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
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419
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420 // - TX timings ---
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421 // - TX down:
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422 // The times below are offsets to when BULENA goes down
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423
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424 #if (PA_CTRL_INT == 1)
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425 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
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426 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
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427 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
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428 #endif
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429
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430 #if (PA_CTRL_INT == 0)
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431 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
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432 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
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433 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
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434 #endif
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435
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436 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
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437 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
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438
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439 // - TX up:
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440 // The times below are offsets to when BULENA goes high
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441 //burst data comes here
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442 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
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443 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
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444
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445 #if (PA_CTRL_INT == 0)
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446 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
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447 #endif
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448
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449 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
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450 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
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451 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
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452 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
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453 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
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454 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
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455 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
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456 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
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457 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
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458 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
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459 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
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460 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
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461