FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/tpudrv/tpudrv61.h @ 905:841982f31be3
lcdemu: got to input lines
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Mon, 07 Sep 2015 08:51:02 +0000 |
parents | 660e83f13cab |
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rev | line source |
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1 /****************** Revision Controle System Header *********************** |
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2 * GSM Layer 1 software |
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3 * Copyright (c) Texas Instruments 1998 |
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4 * |
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5 * Filename tpudrv61.h |
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6 * Version 1.0 |
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7 * Date June 1st, 2005 |
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8 * |
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9 ****************** Revision Controle System Header ***********************/ |
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10 //FLEXIBLE ADC... |
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11 #undef VARIABLE_ADC_ON_TX |
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12 //VARIABLE_ADC_ON_TX- represents the number of symbols before TRF_T11 (the time where the PA is disabled) |
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13 //the ADC conversion should be performed. VARIABLE_ADC_ON_TX- has a valid range from 14 to 155 symbols. |
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14 //Hence, to use the fix, VARIABLE_ADC_ON_TX- must be defined to a value between 14 and 155, compile time. |
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15 //This will cause the ADC conversion offset (TRF_T9) to be calculated by the following equation: |
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16 //TRF_T9 = TRF_T11-VARIABLE_ADC_ON_TX*4 |
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17 //The customer is expected to use a value of 76. If this compile flag is not set, the ADC conversion offset (TRF_T9) |
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18 // is set to a default value of 14 symbols before TXEN is disabled (i.e. the default timing is 40 qbit before the |
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19 // TX down time anchor and 20 qb before the last tail bit). |
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20 #define VARIABLE_ADC_ON_TX 76 |
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21 |
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22 #if(L1_RF_KBD_FIX == 1) |
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23 // Keyboard disable config: |
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24 #define L1_KBD_DIS_RX_NB 1 |
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25 #define L1_KBD_DIS_RX_SB 1 |
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26 #define L1_KBD_DIS_RX_FB 1 |
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27 #define L1_KBD_DIS_RX_FB26 1 |
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28 #define L1_KBD_DIS_RX_MS 1 |
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29 #define L1_KBD_DIS_TX_NB 1 |
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30 #define L1_KBD_DIS_TX_RA 1 |
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31 |
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32 #define KBD_DISABLED 1 |
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33 |
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34 #endif/*(L1_RF_KBD_FIX == 1)*/ |
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35 |
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36 //Fixed declaration of script numbers |
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37 #define DRP_REG_ON (0x0000) |
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38 #define DRP_TX_ON (0x0001) |
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39 #define DRP_RX_ON (0x0002) |
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40 #define DRP_TEMP_CONV (0x0003) |
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41 #define DRP_ROC (0x0004) |
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42 #define DRP_REG_OFF (0x0007) |
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43 #define DRP_AFC (0x000D) |
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44 #define DRP_IDLE (0x000F) |
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45 |
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46 #define SCRIPT_EN (0x3080) |
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47 |
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48 #define START_SCRIPT(script_nb) (SCRIPT_EN | script_nb) |
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49 |
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50 // IF settings |
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51 #define IF_100KHZ_DRP 0 |
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52 #define IF_120KHZ_DRP 1 |
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53 |
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54 // Gain Compensation Enable/Disable |
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55 #define GAIN_COMP_DISABLE (0x0) //Default |
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56 #define GAIN_COMP_ENABLE (0x1) |
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57 |
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58 // AFE Gains Definition |
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59 #define AFE_LOW_GAIN (0x0) // 11 dB |
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60 #define AFE_HIGH_GAIN (0x1) // 38 dB |
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61 |
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62 // ABE Gains Definition |
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63 #define ABE_0_DB (0x0) |
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64 #define ABE_2_DB (0x1) |
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65 #define ABE_5_DB (0x2) |
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66 #define ABE_8_DB (0x3) |
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67 #define ABE_11_DB (0x4) |
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68 #define ABE_14_DB (0x5) |
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69 #define ABE_17_DB (0x6) |
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70 #define ABE_20_DB (0x7) |
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71 #define ABE_23_DB (0x8) |
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72 |
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73 // Switched Cap Filter Corner Freq Defition |
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74 #define SCF_270KHZ 0 |
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75 #define SCF_400KHZ 1 |
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76 |
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77 // Retiming definition |
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78 #define RETIM_DISABLE (0x0000) |
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79 #define RETIM_TX_ONLY (0x0001) |
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80 #define RETIM_RX_ONLY (0x0002) |
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81 #define RETIM_FULL (0x0003) |
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82 |
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83 // IF settings for DSP |
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84 #define IF_100KHZ_DSP 2 |
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85 #define IF_120KHZ_DSP 1 |
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86 |
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87 // DCO algo settings |
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88 #define DCO_IF_100KHZ 1 |
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89 #define DCO_IF_0KHZ 2 |
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90 #define DCO_IF_0KHZ_100KHZ 3 |
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91 #define DCO_NONE 0 |
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92 |
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93 |
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94 //--- Configuration values |
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95 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0 |
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96 // This is also used in l1_rf14h to select the SWAP_IQ |
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97 |
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98 |
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99 //- Bit definitions for TST register programings, etc |
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100 #define BIT_0 0x000001 |
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101 #define BIT_1 0x000002 |
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102 #define BIT_2 0x000004 |
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103 #define BIT_3 0x000008 |
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104 #define BIT_4 0x000010 |
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105 #define BIT_5 0x000020 |
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106 #define BIT_6 0x000040 |
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107 #define BIT_7 0x000080 |
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108 #define BIT_8 0x000100 |
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109 #define BIT_9 0x000200 |
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110 #define BIT_10 0x000400 |
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111 #define BIT_11 0x000800 |
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112 #define BIT_12 0x001000 |
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113 #define BIT_13 0x002000 |
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114 #define BIT_14 0x004000 |
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115 #define BIT_15 0x008000 |
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116 #define BIT_16 0x010000 |
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117 #define BIT_17 0x020000 |
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118 #define BIT_18 0x040000 |
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119 #define BIT_19 0x080000 |
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120 #define BIT_20 0x100000 |
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121 #define BIT_21 0x200000 |
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122 #define BIT_22 0x400000 |
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123 #define BIT_23 0x800000 |
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124 |
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125 |
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126 //- Base REGISTER definitions - |
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127 |
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128 //- RF signals connected to TSPACT - |
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129 #define RX_START BIT_0 // RX_START of DRP2 |
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130 #define TX_START BIT_1 // TX_START of DRP2 modulator |
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131 #define START_APC BIT_2 // Start of the APC module |
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132 #define LDO_EN BIT_3 // Activation of the internal LDO inside the APC bloc |
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133 #if(L1_RF_KBD_FIX == 1) |
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134 #define KBD_DIS_TSPACT BIT_4 // Disable keyboard |
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135 #endif |
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136 #define APC_EN BIT_5 // Enable of the APC module |
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137 #define START_ADC BIT_0 // Activation of the Triton ADC |
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138 #define B3 BIT_3 // Control of the RFMD TX module |
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139 #define B1 BIT_5 // Control of the RFMD TX module |
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140 #define TX_EN BIT_6 // Control of the RFMD TX module |
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141 #define B2 BIT_7 // Control of the RFMD TX module |
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142 |
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143 #define TXM_SLEEP (0) // To avoid leakage during Deep-Seep |
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144 |
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145 // DRP write register |
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146 #define OCP_DATA_MSB 0x05 |
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147 #define OCP_DATA_LSB 0x04 |
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148 #define OCP_ADDRESS_MSB 0x0B |
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149 #define OCP_ADDRESS_LSB 0x0A |
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150 #define OCP_ADDRESS_START 0x01 |
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151 |
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152 // TSPACT |
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153 #define REG_SPI_ACT_U 0x07 |
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154 #define REG_SPI_ACT_L 0x06 |
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155 |
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156 // 3-band config |
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157 // RX_UP/DOWN and TX_UP/DOWN |
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158 #define RU_900 ( B1 | B3 ) |
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159 #define RD_900 ( B1 | B3 ) |
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160 #define TU_900 ( TX_EN | B1 | B3 ) |
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161 #define TD_900 ( B1 | B3 ) |
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162 |
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163 #define RU_850 ( B3 ) |
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164 #define RD_850 ( B3 ) |
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165 #define TU_850 ( TX_EN | B3 ) |
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166 #define TD_850 ( B3 ) |
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167 |
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168 #define RU_1800 ( B2 | B3 ) |
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169 #define RD_1800 ( B2 | B3 ) |
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170 #define TU_1800 ( TX_EN | B1 | B2 | B3 ) |
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171 #define TD_1800 ( B2 | B3 ) |
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172 |
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173 |
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174 #define RU_1900 ( B1 | B2 | B3 ) |
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175 #define RD_1900 ( B1 | B2 | B3 ) |
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176 #define TU_1900 ( TX_EN | B1 | B2 | B3 ) |
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177 #define TD_1900 ( B1 | B2 | B3 ) |
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178 |
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179 |
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180 |
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181 |
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182 //--- TIMINGS ---------------------------------------------------------- |
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183 |
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184 /*------------------------------------------*/ |
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185 /* Download delay values */ |
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186 /*------------------------------------------*/ |
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187 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12) |
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188 |
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189 #define T TPU_CLOCK_RANGE |
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190 |
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191 |
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192 // - TPU instruction into TSP timings --- |
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193 // 1 tpu instruction = 1 qbit |
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194 #define DLT_1 1 // 1 tpu instruction = 1 qbit |
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195 #define DLT_2 2 // 2 tpu instruction = 2 qbit |
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196 #define DLT_3 3 // 3 tpu instruction = 3 qbit |
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197 #define DLT_4 4 // 4 tpu instruction = 4 qbit |
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198 |
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199 // - TPU command execution + serialization length --- |
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200 #define DLT_4B 5 // 5*move |
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201 |
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202 |
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203 // - INIT (delta or DLT) timings --- |
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204 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON |
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205 #define DLT_I2 200 // Regulators turn on time |
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206 #define DLT_I3 5 // Time required to set RF_SER_ON |
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207 #define DLT_I4 110 // Regulator Turn-ON time |
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208 |
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209 |
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210 // - tdt & rdt --- |
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211 // MAX GSM (not GPRS) rdt and tdt values are... |
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212 //#define rdt 380 // MAX GSM rx delta timing |
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213 //#define tdt 400 // MAX GSM tx delta timing |
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214 // but current rdt and tdt values are... |
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215 #define rdt 0 // rx delta timing |
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216 #define tdt 0 // tx delta timing |
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217 |
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218 // - RX timings --- |
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219 // - RX down: |
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220 // Flexible TPU Timings .... |
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221 |
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222 /************************************/ |
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223 /* Timing for TPU prog */ |
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224 /************************************/ |
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225 #if ( L1_TPU_DEV == 0) |
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226 #define APC_RAMP_UP_TIME 20 // maximum time for ramp up |
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227 #define APC_RAMP_DELAY 6 // minimum ramp up delay APCDEL |
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228 #define APC_RAMP_DOWN_TIME 20 // maximum ramp down time |
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229 #endif |
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230 |
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231 |
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232 #if ( L1_TPU_DEV == 1) |
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233 extern WORD16 rf_tx_tpu_timings[]; |
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234 extern WORD16 rf_rx_tpu_timings[]; |
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235 |
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236 //define for TPU Dev Mode via the arrays so that they can be tweaked later for Rx & Tx |
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237 |
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238 |
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239 |
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240 #define TRF_T1 rf_tx_tpu_timings[0] |
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241 #define TRF_T2 rf_tx_tpu_timings[1] |
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242 #define TRF_T3 rf_tx_tpu_timings[2] |
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243 #define TRF_T4 rf_tx_tpu_timings[3] |
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244 #define TRF_T5 rf_tx_tpu_timings[4] |
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245 #define TRF_T6 rf_tx_tpu_timings[5] |
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246 #define TRF_T7 rf_tx_tpu_timings[6] |
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247 #define TRF_T8 rf_tx_tpu_timings[7] |
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248 #define TRF_T9 rf_tx_tpu_timings[8] |
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249 #define TRF_T10 rf_tx_tpu_timings[9] |
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250 #define TRF_T11 rf_tx_tpu_timings[10] |
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251 #define TRF_T12 rf_tx_tpu_timings[11] |
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252 #define TRF_T13 rf_tx_tpu_timings[12] |
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253 #define TRF_T14 rf_tx_tpu_timings[13] |
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254 #define TRF_T15 rf_tx_tpu_timings[14] |
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255 #define TRF_T16 rf_tx_tpu_timings[15] |
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256 #define TRF_T17 rf_tx_tpu_timings[16] |
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257 #define TRF_T18 rf_tx_tpu_timings[17] |
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258 #define TRF_T19 rf_tx_tpu_timings[18] |
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259 #define TRF_T20 rf_tx_tpu_timings[19] |
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260 #define TRF_T21 rf_tx_tpu_timings[20] |
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261 #define TRF_T22 rf_tx_tpu_timings[21] |
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262 #define TRF_T23 rf_tx_tpu_timings[22] |
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263 #define TRF_T24 rf_tx_tpu_timings[23] |
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264 #define TRF_T25 rf_tx_tpu_timings[24] |
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265 #define TRF_T26 rf_tx_tpu_timings[25] |
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266 #define TRF_T27 rf_tx_tpu_timings[26] |
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267 #define TRF_T28 rf_tx_tpu_timings[27] |
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268 #define TRF_T29 rf_tx_tpu_timings[28] |
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269 #define TRF_T30 rf_tx_tpu_timings[29] |
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270 #define TRF_T31 rf_tx_tpu_timings[30] |
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271 #define TRF_T32 rf_tx_tpu_timings[31] |
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272 |
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273 |
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274 #define TRF_R1 rf_rx_tpu_timings[0] |
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275 #define TRF_R2 rf_rx_tpu_timings[1] |
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276 #define TRF_R3 rf_rx_tpu_timings[2] |
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277 #define TRF_R4 rf_rx_tpu_timings[3] |
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278 #define TRF_R5 rf_rx_tpu_timings[4] |
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279 #define TRF_R6 rf_rx_tpu_timings[5] |
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280 #define TRF_R7 rf_rx_tpu_timings[6] |
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281 #define TRF_R8 rf_rx_tpu_timings[7] |
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282 #define TRF_R9 rf_rx_tpu_timings[8] |
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283 #define TRF_R10 rf_rx_tpu_timings[9] |
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284 #define TRF_R11 rf_rx_tpu_timings[10] |
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285 #define TRF_R12 rf_rx_tpu_timings[11] |
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286 #define TRF_R13 rf_rx_tpu_timings[12] |
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287 #define TRF_R14 rf_rx_tpu_timings[13] |
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288 #define TRF_R15 rf_rx_tpu_timings[14] |
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289 #define TRF_R16 rf_rx_tpu_timings[15] |
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290 #define TRF_R17 rf_rx_tpu_timings[16] |
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291 #define TRF_R18 rf_rx_tpu_timings[17] |
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292 #define TRF_R19 rf_rx_tpu_timings[18] |
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293 #define TRF_R20 rf_rx_tpu_timings[19] |
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294 #define TRF_R21 rf_rx_tpu_timings[20] |
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295 #define TRF_R22 rf_rx_tpu_timings[21] |
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296 #define TRF_R23 rf_rx_tpu_timings[22] |
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297 #define TRF_R24 rf_rx_tpu_timings[23] |
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298 #define TRF_R25 rf_rx_tpu_timings[24] |
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299 #define TRF_R26 rf_rx_tpu_timings[25] |
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300 #define TRF_R27 rf_rx_tpu_timings[26] |
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301 #define TRF_R28 rf_rx_tpu_timings[27] |
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302 #define TRF_R29 rf_rx_tpu_timings[28] |
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303 #define TRF_R30 rf_rx_tpu_timings[29] |
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304 #define TRF_R31 rf_rx_tpu_timings[30] |
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305 #define TRF_R32 rf_rx_tpu_timings[31] |
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306 |
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307 //Flexi ABB Delays |
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308 // The existing #defines in the code would have to be removed and the definitions done here. |
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309 |
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310 extern WORD16 rf_flexi_abb_delays[]; |
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311 |
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312 |
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313 |
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314 #ifdef APC_RAMP_UP_TIME |
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315 #undef APC_RAMP_UP_TIME |
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316 #endif |
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317 #define APC_RAMP_UP_TIME rf_flexi_abb_delays[1] //default 32 |
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318 |
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319 |
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320 #ifdef DL_ABB_DELAY |
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321 #undef DL_ABB_DELAY |
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322 #endif |
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323 #define DL_ABB_DELAY (rf_flexi_abb_delays[2]) // ( 32L + 4L) |
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324 |
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325 |
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326 #ifdef UL_ABB_DELAY |
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327 #undef UL_ABB_DELAY |
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328 #endif |
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329 #define UL_ABB_DELAY rf_flexi_abb_delays[3] //12 |
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330 |
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331 #ifdef UL_DELAY_1RF |
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332 #undef UL_DELAY_1RF |
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333 #endif |
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334 #define UL_DELAY_1RF rf_flexi_abb_delays[4] //0 |
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335 |
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336 #ifdef UL_DELAY_2RF |
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337 #undef UL_DELAY_2RF |
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338 #endif |
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339 #define UL_DELAY_2RF rf_flexi_abb_delays[5] //0 |
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340 |
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341 #ifdef APCDEL_DOWN |
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342 #undef APCDEL_DOWN |
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343 #endif |
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344 #define APCDEL_DOWN rf_flexi_abb_delays[6] //3//3 |
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345 |
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346 #ifdef APCDEL_UP |
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347 #undef APCDEL_UP |
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348 #endif |
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349 #define APCDEL_UP rf_flexi_abb_delays[7] //24 |
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350 |
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351 #ifdef GUARD_BITS |
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352 #undef GUARD_BITS |
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353 #endif |
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354 #define GUARD_BITS rf_flexi_abb_delays[8] //7 |
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355 |
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356 #ifdef SETUP_AFC_AND_RF |
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357 #undef SETUP_AFC_AND_RF |
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358 #endif |
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359 #define SETUP_AFC_AND_RF rf_flexi_abb_delays[9] //6 |
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360 |
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361 #ifdef SERV_OFFS_REST_LOAD |
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362 #undef SERV_OFFS_REST_LOAD |
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363 #endif |
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364 #define SERV_OFFS_REST_LOAD rf_flexi_abb_delays[10] // 1L |
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365 |
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366 #ifdef TA_MAX |
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367 #undef TA_MAX |
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368 #endif |
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369 #define TA_MAX rf_flexi_abb_delays[11] // ( 63L * 4L ) |
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370 |
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371 #ifdef PRG_TX |
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372 #undef PRG_TX |
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373 #endif |
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374 #define PRG_TX rf_flexi_abb_delays[12] // (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) |
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375 |
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376 #ifdef EPSILON_OFFS |
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377 #undef EPSILON_OFFS |
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378 #endif |
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379 #define EPSILON_OFFS rf_flexi_abb_delays[14] // 2L |
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380 |
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381 #ifdef EPSILON_MEAS |
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382 #undef EPSILON_MEAS |
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383 #endif |
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384 #define EPSILON_MEAS rf_flexi_abb_delays[15]//20L |
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385 |
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386 #ifdef EPSILON_SYNC |
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387 #undef EPSILON_SYNC |
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388 #endif |
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389 #define EPSILON_SYNC rf_flexi_abb_delays[16] //10L |
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390 |
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391 #ifdef APC_RAMP_DOWN_TIME |
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392 #undef APC_RAMP_DOWN_TIME |
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393 #endif |
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394 #define APC_RAMP_DOWN_TIME rf_flexi_abb_delays[17] //32 |
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395 |
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396 #ifdef APC_RAMP_DELAY |
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397 #undef APC_RAMP_DELAY |
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398 #endif |
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399 #define APC_RAMP_DELAY rf_flexi_abb_delays[18] //6 |
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400 #endif //L1_TPU_DEV |
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401 // End Flexible TPU Timings, ABB DElays |
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402 |
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403 #if ( L1_TPU_DEV == 0) |
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404 // - RX timings --- |
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405 // - RX down: |
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406 #if (L1_MADC_ON == 1) |
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407 #define TRF_R8 (PROVISION_TIME - 170 - DLT_4B - rdt ) // for doing MADC |
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408 #endif |
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409 // The times below are offsets to when BDLENA goes down |
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410 #define TRF_R7 ( 2 - DLT_4B ) // Power down RF (idle script) |
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411 // TRF_R6 not use, warning timing TRF_R6 > TRF_R7 |
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412 #define TRF_R6 ( -20 - DLT_4B) // Disable RX Start and RF switch |
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413 |
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414 // - RX up: |
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415 // The times below are offsets to when BDLENA goes high |
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416 // Burst data comes here |
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417 #define TRF_R5 (PROVISION_TIME - 19 - DLT_1 ) // Enable RX_START |
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418 #define TRF_R4 (PROVISION_TIME - 39 - DLT_1 - rdt ) // Set RF switch for RX in selected band |
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419 #if(L1_RF_KBD_FIX == 1) |
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420 #define TRF_R3_1 (PROVISION_TIME - 89 - DLT_1 - rdt ) // Disable keyboard |
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421 #endif |
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422 #define TRF_R3 (PROVISION_TIME - 190 - DLT_4B - rdt ) // RX_ON |
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423 #define TRF_R2 (PROVISION_TIME - 197 - DLT_4B - rdt ) // Select the AGC & LNA gains |
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424 #define TRF_R1 (PROVISION_TIME - 203 - DLT_4B - rdt ) // Set RX Synth channel |
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425 |
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426 |
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427 |
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428 // - TX timings --- |
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429 // - TX down: |
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430 // The times below are offsets to when TXSTART goes down |
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431 #define TRF_T13 ( 25 - DLT_1 ) // |
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432 #define TRF_T12 ( 23 - DLT_4B ) // |
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433 #define TRF_T11 ( 16 - DLT_1 ) // |
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434 #define TRF_T10 ( 0 - DLT_1 ) // |
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435 #ifdef VARIABLE_ADC_ON_TX |
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436 #define TRF_T9 (TRF_T11-VARIABLE_ADC_ON_TX*4) |
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437 #else |
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438 #define TRF_T9 ( - 40 - DLT_1 ) // |
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439 #endif |
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440 |
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441 // - TX up: |
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442 // The times below are offsets to when TXSTART goes high |
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443 //burst data comes here |
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444 #define TRF_T8 ( 18 - DLT_1 ) // |
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445 #define TRF_T7 ( 12 - DLT_1 ) // |
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446 #define TRF_T6 ( 6 - DLT_1 ) // |
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447 #define TRF_T5 ( 0 - DLT_1 ) // |
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448 #define TRF_T4 ( - 100 - DLT_1 ) // |
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449 #if(L1_RF_KBD_FIX == 1) |
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450 #define TRF_T3_1 (-215 -DLT_1 ) // Disable keyboard |
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451 #endif |
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452 #define TRF_T3 ( - 225 - DLT_1 ) // Set APC_LDO enabled |
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453 #define TRF_T2 ( - 235 - DLT_4B - tdt ) // Power ON TX |
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454 #define TRF_T1 ( - 255 - DLT_4B - tdt ) // Set TX synth |
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455 |
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456 #endif // Non TPU DEV |
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457 |
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458 |
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459 |