FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/sysglue/irqfiq.S @ 203:99c234bf6a9b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
fc-loadtool flash ID check: definitions created
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 23 Dec 2013 07:26:37 +0000
parents afceeeb2cba1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
114
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 /*
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 * This module contains the assembly shells for IRQ and FIQ, separated
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 * from the architectured vectors only by some simple unconditional
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
4 * branch instructions.
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
5 *
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
6 * Note that TI's way of handling interrupts sacrifices Nucleus' ability
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
7 * to nest interrupts and minimize the IRQ-disabled window: if my (Falcon's)
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
8 * understanding is correct, TI's code leaves all further IRQs disabled
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
9 * for the full execution duration of an IRQ handler. (IRQ handlers are
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
10 * really LISRs, but TI's GSM fw does not use Nucleus' LISR framework.)
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
11 */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
12
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
13 .section iram.text,"ax",%progbits
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
14 .code 32
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
15
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
16 .globl _INT_IRQ
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
17 _INT_IRQ:
132
2c5160a9d652 nuc-fw: switched from nucdemo to Riviera, got some serial output
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
18 STMDB sp!,{r0-r4} @ used to be a1-a4
114
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
19
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
20 /*
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
21 * Thanks to TI for discovering and documenting this apparent ARM7TDMI bug:
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
22
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
23 BUG correction 1st part -------------------
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
24 It looks like there is an issue with ARM7 IRQ masking in the CPSR register
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
25 which leads to crashes in Nucleus+ scheduler.
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
26 Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
27 prevent from having an interrupt after the execution of the third line (I mean execution, not
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
28 fetch).
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
29 MRS a1,CPSR ; Pickup current CPSR
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
30 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
31 MSR CPSR,a1 ; Lockout interrupts
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
32 * IRQ INTERRUPT ! *
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
33 Next instructions...
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
34
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
35 SW workaround:
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
36 When a task is interrupted at this point an interrupted context is stored on its task and will
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
37 be resumed later on at the next instruction but to make a long story short it leads to some
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
38 problem as the OS does not expect to be interrupted there.
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
39 Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
40 but that the IRQ is still triggered (has been hardwarewise requested during the instruction
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
41 exectution by the ARM7 core?)
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
42 */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
43
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
44 MRS a1,spsr @ check for the IRQ bug:
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
45 TST a1,#0x80 @ if the I - flag is set,
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
46 BNE IRQBUG @ then postpone execution of this IRQ
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
47 /* Bug correction 1st part end --------------- */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
48
132
2c5160a9d652 nuc-fw: switched from nucdemo to Riviera, got some serial output
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
49 SUB r4,lr,#4 @ Save IRQ's lr (return address)
114
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
50 BL TCT_Interrupt_Context_Save @ Call context save routine
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
51
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
52 BL IQ_IRQ_isr @ Call int. service routine
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
53
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
54 /* IRQ interrupt processing is complete. Restore context- Never
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
55 returns! */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
56 B TCT_Interrupt_Context_Restore
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
57
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
58 /* BUG correction 2nd part ------------------ */
132
2c5160a9d652 nuc-fw: switched from nucdemo to Riviera, got some serial output
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
59 IRQBUG: LDMFD sp!,{r0-r4} @ return from interrupt
114
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
60 SUBS pc,r14,#4
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
61 /* BUG correction 2nd part end -------------- */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
62
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
63 .globl _INT_FIQ
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
64 _INT_FIQ:
132
2c5160a9d652 nuc-fw: switched from nucdemo to Riviera, got some serial output
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
65 STMDB sp!,{r0-r4} @ used to be a1-a4
2c5160a9d652 nuc-fw: switched from nucdemo to Riviera, got some serial output
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
66 SUB r4,lr,#4 @ Save FIQ's lr (return address)
114
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
67 BL TCT_Interrupt_Context_Save @ Call context save routine
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
68
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
69 BL IQ_FIQ_isr @ Call the FIQ ISR
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
70
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
71 /* FIQ interrupt processing is complete. Restore context- Never
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
72 returns! */
17b0511b243c nuc-fw: continuing lowest-level BSP integration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
73 B TCT_Interrupt_Context_Restore