annotate gsm-fw/bsp/abb+spi/Makefile @ 992:a7b0b426f9ca

target-utils: boot ROM UART autodetection revamped The new implementation should work with both the familiar Calypso C035 boot ROM version found in our regular targets as well as the older Calypso F741979B version found on the vintage D-Sample board.
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Wed, 30 Dec 2015 21:28:41 +0000
parents 6fd70825db76
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
154
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 CC= arm-elf-gcc
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 CFLAGS= -O2 -fno-builtin -mthumb-interwork -mthumb
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 LD= arm-elf-ld
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
4
590
05342cadbaf1 gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 157
diff changeset
5 sinclude ../../include/config.mk
05342cadbaf1 gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 157
diff changeset
6
157
e48ea5875df7 gsm-fw: SPI task code compiles and links
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 154
diff changeset
7 OBJS= abb.o spi_api.o spi_drv.o spi_env.o spi_process.o spi_task.o
154
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
8
590
05342cadbaf1 gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 157
diff changeset
9 ifeq (${CONFIG_INCLUDE_L1},1)
591
6fd70825db76 gsm-fw/bsp/abb+spi: abb_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 590
diff changeset
10 OBJS+= abb_core_inth.o abb_inth.o
590
05342cadbaf1 gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 157
diff changeset
11 endif
05342cadbaf1 gsm-fw/bsp/abb+spi: abb_core_inth.c compiles with L1 enabled
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 157
diff changeset
12
154
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
13 HDRS= abb.h abb_core_inth.h abb_inline.h abb_inth.h spi_api.h spi_drv.h \
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
14 spi_env.h spi_pool_size.h spi_process.h spi_task.h
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
15
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
16 all: xipcode.o
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
17
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
18 ${OBJS}: ${HDRS}
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
19
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
20 xipcode.o: ${OBJS}
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
21 ${LD} -r -o $@ ${OBJS}
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
22
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
23 clean:
47754cdb6248 abb.c compiles!
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
24 rm -f *.[oa] *errs