FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/abb+spi/abb.c @ 992:a7b0b426f9ca
target-utils: boot ROM UART autodetection revamped
The new implementation should work with both the familiar Calypso C035
boot ROM version found in our regular targets as well as the older
Calypso F741979B version found on the vintage D-Sample board.
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Wed, 30 Dec 2015 21:28:41 +0000 |
parents | 1c0033c2fe33 |
children |
rev | line source |
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588
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1 /******************************************************************************/ |
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ |
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3 /* */ |
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */ |
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This*/ |
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6 /* product is protected under copyright law and trade secret law as an*/ |
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All*/ |
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8 /* rights reserved. */ |
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9 /* */ |
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10 /* */ |
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11 /* Filename : abb.c */ |
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12 /* */ |
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13 /* Description : Functions to drive the ABB device. */ |
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14 /* The Serial Port Interface is used to connect the TI */ |
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15 /* Analog BaseBand (ABB). */ |
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16 /* It is assumed that the ABB is connected as the SPI */ |
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17 /* device 0. */ |
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18 /* */ |
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19 /* Author : Pascal PUEL */ |
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20 /* */ |
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21 /* Version number : 1.3 */ |
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22 /* */ |
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23 /* Date and time : 08/22/03 */ |
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24 /* */ |
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25 /* Previous delta : Creation */ |
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26 /* */ |
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27 /******************************************************************************/ |
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28 |
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29 #include "../../include/config.h" |
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30 #include "../../include/sys_types.h" |
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31 #include "../../riviera/rv/general.h" |
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32 #include "../../nucleus/nucleus.h" // for NUCLEUS functions and types |
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33 |
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34 #include "../../L1/include/l1_confg.h" |
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35 #include "../../L1/include/l1_macro.h" |
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36 |
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37 #include "abb.h" |
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38 #include "../clkm.h" // for wait_ARM_cycles function |
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39 #include "abb_inline.h" |
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40 #include "../ulpd.h" // for FRAME_STOP definition |
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41 |
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42 #include "../../L1/include/l1_types.h" |
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43 |
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44 #if 0 // FreeCalypso |
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45 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function |
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46 #endif |
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47 |
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48 #if (VCXO_ALGO == 1) |
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49 #include "../../L1/include/l1_ctl.h" |
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50 #endif |
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51 |
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52 #if (RF_FAM == 35) |
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53 #include "../../L1/cust0/l1_rf35.h" |
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54 #endif |
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55 |
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56 #if (RF_FAM == 12) |
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57 #include "../../L1/tpudrv/tpudrv12.h" |
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58 #include "../../L1/cust0/l1_rf12.h" |
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59 #endif |
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60 |
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61 #if (RF_FAM == 10) |
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62 #include "../../L1/cust0/l1_rf10.h" |
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63 #endif |
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64 |
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65 #if (RF_FAM == 8) |
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66 #include "../../L1/cust0/l1_rf8.h" |
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67 #endif |
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68 |
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69 #if (RF_FAM == 2) |
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70 #include "../../L1/cust0/l1_rf2.h" |
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71 #endif |
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72 |
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73 #if (ABB_SEMAPHORE_PROTECTION) |
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74 |
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75 static NU_SEMAPHORE abb_sem; |
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76 |
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77 /*-----------------------------------------------------------------------*/ |
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78 /* ABB_Sem_Create() */ |
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79 /* */ |
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80 /* This function creates the Nucleus semaphore to protect ABB accesses */ |
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81 /* against preemption. */ |
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82 /* No check on the result. */ |
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83 /* */ |
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84 /*-----------------------------------------------------------------------*/ |
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85 void ABB_Sem_Create(void) |
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86 { |
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87 // create a semaphore with an initial count of 1 and with FIFO type suspension. |
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88 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); |
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89 } |
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90 |
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91 #endif // ABB_SEMAPHORE_PROTECTION |
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92 |
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93 /*-----------------------------------------------------------------------*/ |
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94 /* ABB_Wait_IBIC_Access() */ |
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95 /* */ |
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96 /* This function waits for the first IBIC access. */ |
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97 /* */ |
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98 /*-----------------------------------------------------------------------*/ |
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99 void ABB_Wait_IBIC_Access(void) |
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100 { |
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101 #if (ANALOG ==1) |
148
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102 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access |
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103 // (i.e wait 60us + 10% security marge = 66us) |
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104 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); |
154
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152
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105 #elif ((ANALOG ==2) || (ANALOG == 3)) |
148
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106 // Wait 6 x 32 KHz clock cycles for first IBIC access |
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107 // (i.e wait 187us + 10% security marge = 210us) |
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108 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); |
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109 #endif |
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110 } |
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111 |
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112 |
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113 |
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114 /*-----------------------------------------------------------------------*/ |
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115 /* ABB_Write_Register_on_page() */ |
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116 /* */ |
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117 /* This function manages all the spi serial transfer to write to an */ |
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118 /* ABB register on a specified page. */ |
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119 /* */ |
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120 /*-----------------------------------------------------------------------*/ |
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121 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) |
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122 { |
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123 volatile SYS_UWORD16 status; |
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124 |
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125 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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126 SPI_Ready_for_WR |
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127 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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128 |
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129 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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130 |
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131 // check if the semaphore has been correctly created and try to obtain it. |
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132 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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133 // as soon as the semaphore is released. |
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134 if(&abb_sem != 0) |
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135 { |
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136 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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137 } |
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138 #endif // ABB_SEMAPHORE_PROTECTION |
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139 |
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140 // set the ABB page for register access |
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141 ABB_SetPage(page); |
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142 |
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143 // Write value in reg_id |
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144 ABB_WriteRegister(reg_id, value); |
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145 |
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146 // set the ABB page for register access at page 0 |
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147 ABB_SetPage(PAGE0); |
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148 |
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149 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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150 // release the semaphore only if it has correctly been created. |
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151 if(&abb_sem != 0) |
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152 { |
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153 NU_Release_Semaphore(&abb_sem); |
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154 } |
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155 #endif // ABB_SEMAPHORE_PROTECTION |
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156 |
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157 // Stop the SPI clock |
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158 #ifdef SPI_CLK_LOW_POWER |
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159 SPI_CLK_DISABLE |
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160 #endif |
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161 } |
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162 |
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163 |
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164 /*-----------------------------------------------------------------------*/ |
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165 /* ABB_Read_Register_on_page() */ |
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166 /* */ |
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167 /* This function manages all the spi serial transfer to read one */ |
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168 /* ABB register on a specified page. */ |
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169 /* */ |
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170 /* Returns the real data value of the register. */ |
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171 /* */ |
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172 /*-----------------------------------------------------------------------*/ |
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173 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) |
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174 { |
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175 volatile SYS_UWORD16 status; |
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176 SYS_UWORD16 reg_val; |
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177 |
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178 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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179 SPI_Ready_for_RDWR |
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180 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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181 |
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182 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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183 |
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184 // check if the semaphore has been correctly created and try to obtain it. |
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185 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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186 // as soon as the semaphore is released. |
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187 if(&abb_sem != 0) |
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188 { |
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189 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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190 } |
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191 #endif // ABB_SEMAPHORE_PROTECTION |
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192 |
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193 /* set the ABB page for register access */ |
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194 ABB_SetPage(page); |
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195 |
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196 /* Read selected ABB register */ |
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197 reg_val = ABB_ReadRegister(reg_id); |
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198 |
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199 /* set the ABB page for register access at page 0 */ |
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200 ABB_SetPage(PAGE0); |
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201 |
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202 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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203 // release the semaphore only if it has correctly been created. |
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204 if(&abb_sem != 0) |
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205 { |
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206 NU_Release_Semaphore(&abb_sem); |
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207 } |
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208 #endif // ABB_SEMAPHORE_PROTECTION |
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209 |
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210 // Stop the SPI clock |
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211 #ifdef SPI_CLK_LOW_POWER |
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212 SPI_CLK_DISABLE |
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213 #endif |
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214 |
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215 return (reg_val); // Return result |
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216 } |
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217 |
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218 /*------------------------------------------------------------------------*/ |
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219 /* ABB_free_13M() */ |
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220 /* */ |
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221 /* This function sets the 13M clock working in ABB. A wait loop */ |
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222 /* is required to allow first slow access to ABB clock register. */ |
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223 /* */ |
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224 /* WARNING !! : this function must not be protected by semaphore !! */ |
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225 /* */ |
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226 /*------------------------------------------------------------------------*/ |
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227 void ABB_free_13M(void) |
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228 { |
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229 volatile SYS_UWORD16 status; |
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230 |
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231 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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232 SPI_Ready_for_WR |
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233 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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234 |
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235 ABB_SetPage(PAGE0); |
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236 |
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237 // This transmission frees the CLK13 in ABB. |
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238 ABB_WriteRegister(TOGBR2, 0x08); |
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239 |
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240 // Wait for first IBIC access |
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241 ABB_Wait_IBIC_Access(); |
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242 |
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243 // SW Workaround : This transmission has to be done twice. |
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244 ABB_WriteRegister(TOGBR2, 0x08); |
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245 |
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246 // Wait for first IBIC access |
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247 ABB_Wait_IBIC_Access(); |
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248 |
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249 // Stop the SPI clock |
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250 #ifdef SPI_CLK_LOW_POWER |
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251 SPI_CLK_DISABLE |
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252 #endif |
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253 } |
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254 |
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255 |
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256 |
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257 /*------------------------------------------------------------------------*/ |
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258 /* ABB_stop_13M() */ |
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259 /* */ |
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260 /* This function stops the 13M clock in ABB. */ |
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261 /* */ |
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262 /*------------------------------------------------------------------------*/ |
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263 void ABB_stop_13M(void) |
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264 { |
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265 volatile SYS_UWORD16 status; |
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266 |
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267 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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268 SPI_Ready_for_WR |
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269 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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270 |
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271 ABB_SetPage(PAGE0); |
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272 |
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273 // Set ACTIVMCLK = 0. |
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274 ABB_WriteRegister(TOGBR2, 0x04); |
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275 |
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276 // Wait for first IBIC access |
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277 ABB_Wait_IBIC_Access(); |
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278 |
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279 // Stop the SPI clock |
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280 #ifdef SPI_CLK_LOW_POWER |
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281 SPI_CLK_DISABLE |
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282 #endif |
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283 } |
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284 |
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285 |
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286 |
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287 /*------------------------------------------------------------------------*/ |
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288 /* ABB_Read_Status() */ |
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289 /* */ |
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290 /* This function reads and returns the value of VRPCSTS ABB register. */ |
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291 /* */ |
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292 /*------------------------------------------------------------------------*/ |
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293 SYS_UWORD16 ABB_Read_Status(void) |
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294 { |
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295 volatile SYS_UWORD16 status; |
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296 SYS_UWORD16 reg_val; |
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297 |
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298 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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299 SPI_Ready_for_WR |
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300 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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301 |
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302 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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303 |
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304 // check if the semaphore has been correctly created and try to obtain it. |
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305 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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306 // as soon as the semaphore is released. |
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307 if(&abb_sem != 0) |
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308 { |
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309 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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310 } |
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311 #endif // ABB_SEMAPHORE_PROTECTION |
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312 |
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313 ABB_SetPage(PAGE0); |
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314 |
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315 #if (ANALOG == 1) || (ANALOG == 2) |
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316 ABB_SetPage(PAGE0); |
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317 reg_val = ABB_ReadRegister(VRPCSTS); |
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318 #elif (ANALOG == 3) |
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319 ABB_SetPage(PAGE1); |
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320 reg_val = ABB_ReadRegister(VRPCCFG); |
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321 #endif |
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322 |
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323 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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324 // release the semaphore only if it has correctly been created. |
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325 if(&abb_sem != 0) |
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326 { |
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327 NU_Release_Semaphore(&abb_sem); |
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328 } |
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329 #endif // ABB_SEMAPHORE_PROTECTION |
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330 |
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331 // Stop the SPI clock |
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332 #ifdef SPI_CLK_LOW_POWER |
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333 SPI_CLK_DISABLE |
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334 #endif |
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335 |
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336 return (reg_val); |
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337 } |
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338 |
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339 /*------------------------------------------------------------------------*/ |
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340 /* ABB_on() */ |
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341 /* */ |
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342 /* This function configures ABB registers to work in ON condition */ |
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343 /* */ |
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344 /*------------------------------------------------------------------------*/ |
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345 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) |
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346 { |
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347 volatile SYS_UWORD16 status; |
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348 #if ((ANALOG ==2) || (ANALOG == 3)) |
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349 SYS_UWORD32 reg; |
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350 #endif |
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351 |
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352 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 |
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353 if (bRecoveryFlag) |
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354 { |
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355 // RESTITUTE 13MHZ CLOCK TO ABB |
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356 //--------------------------------------------------- |
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357 ABB_free_13M(); |
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358 |
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359 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) |
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360 //--------------------------------------------------- |
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361 ABB_free_13M(); |
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362 } |
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363 |
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364 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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365 SPI_Ready_for_RDWR |
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366 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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367 |
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368 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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369 |
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370 // check if the semaphore has been correctly created and try to obtain it. |
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371 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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372 // as soon as the semaphore is released. |
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373 if(&abb_sem != 0) |
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374 { |
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375 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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376 } |
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377 #endif // ABB_SEMAPHORE_PROTECTION |
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378 |
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379 ABB_SetPage(PAGE0); |
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380 |
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381 // This transmission disables MADC,AFC,VDL,VUL modules. |
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382 ABB_WriteRegister(TOGBR1, 0x0155); |
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383 |
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384 #if (ANALOG == 1) |
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385 // This transmission disables Band gap fast mode Enable BB charge. |
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386 ABB_WriteRegister(VRPCCTL2, 0x1fc); |
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387 |
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388 /* *********** DC/DC enabling selection ************************************************************** */ |
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389 // This transmission changes the register page in OMEGA for usp to pg1. |
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390 ABB_SetPage(PAGE1); |
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391 |
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392 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */ |
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393 { |
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394 SYS_UWORD8 vrpcctrl3_data; |
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395 |
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396 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) |
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397 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035 |
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398 #else |
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399 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 |
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400 #endif |
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401 |
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402 if(modules & DCDC) // check if the DCDC is enabled |
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403 { |
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404 vrpcctrl3_data |= 0x0002; // set DCDCEN |
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405 } |
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406 |
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407 // This access disables the DCDC. |
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408 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); |
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409 } |
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410 |
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411 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ |
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412 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ |
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413 /* ***************************************************************************************************/ |
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414 #if (BOARD==6)&& (ANALOG==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) |
148
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415 // This transmission enables Omega test register. |
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416 ABB_WriteRegister(TAPCTRL, 0x01); |
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417 |
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418 // This transmission select Omega test instruction. |
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419 ABB_WriteRegister(TAPREG, TSPTEST1); |
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420 |
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421 // This transmission disables Omega test register. |
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422 ABB_WriteRegister(TAPCTRL, 0x00); |
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423 #endif |
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424 /* *************************************************************************************************** */ |
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425 |
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426 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue |
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427 { |
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428 // This transmission changes SIM power supply to 3 volts. |
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429 ABB_WriteRegister(VRPCCTRL1, 0x45); |
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430 } |
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431 |
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432 ABB_SetPage(PAGE0); |
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433 |
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434 // This transmission enables selected OMEGA modules. |
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435 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); |
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436 |
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437 if(modules & MADC) // check if the ADC is enabled |
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438 { |
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439 // This transmission connects the resistive divider to MB and BB. |
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440 ABB_WriteRegister(BCICTL1, 0x0005); |
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441 } |
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442 #elif ((ANALOG == 2) || (ANALOG == 3)) |
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443 // Restore the ABB checks and debouncing if start on TESTRESETZ |
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444 |
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445 // This transmission changes the register page in the ABB for usp to pg1. |
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446 ABB_SetPage(PAGE1); |
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447 |
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448 // This transmission sets the AFCCK to CKIN/2. |
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449 ABB_WriteRegister(AFCCTLADD, 0x01); |
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450 |
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451 // This transmission enables the tapreg. |
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452 ABB_WriteRegister(TAPCTRL, 0x01); |
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453 |
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454 // This transmission enables access to page 2. |
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455 ABB_WriteRegister(TAPREG, 0x01b); |
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456 |
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457 // This transmission changes the register page in the ABB for usp to pg2. |
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458 ABB_SetPage(PAGE2); |
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459 |
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460 #if (ANALOG == 2) |
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461 // Restore push button environment |
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462 ABB_WriteRegister(0x3C, 0x07); |
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463 |
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464 #elif (ANALOG == 3) |
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465 |
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466 // Restore push button environment |
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467 ABB_WriteRegister(0x3C, 0xBF); |
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468 |
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469 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ |
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470 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
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471 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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472 #endif |
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473 // This transmission enables access to page 0. |
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474 ABB_SetPage(PAGE0); |
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475 |
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476 // reset bit MSKINT1 , if set by TESTRESET |
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477 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; |
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478 |
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479 ABB_WriteRegister(VRPCSTS, reg); |
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480 |
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481 ABB_SetPage(PAGE2); |
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482 |
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483 // Restore default for BG behavior in sleep mode |
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484 ABB_WriteRegister(VRPCAUX, 0xBF); |
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485 |
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486 // Restore default for deboucing length |
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487 ABB_WriteRegister(VRPCLDO, 0x00F); |
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488 |
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489 // Restore default for INT1 generation, wait time in switch on, checks in switch on |
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490 ABB_WriteRegister(VRPCABBTST, 0x0002); |
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|
491 |
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492 #endif |
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493 |
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494 // This transmission changes the register page in the ABB for usp to pg1. |
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495 ABB_SetPage(PAGE1); |
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|
496 |
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497 // This transmission sets tapinst to id code. |
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498 ABB_WriteRegister(TAPREG, 0x0001); |
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499 |
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500 // This transmission disables TAPREG access. |
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501 ABB_WriteRegister(TAPCTRL, 0x00); |
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502 |
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503 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows |
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504 // This transmission enables BB charge and BB bridge connection for BB measurements. |
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505 ABB_WriteRegister(BCICONF, 0x060); |
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|
506 |
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507 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ |
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508 #if (ANALOG == 3) |
148
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509 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO |
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510 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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511 #endif |
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512 #endif |
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513 |
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|
514 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ |
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515 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
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516 /* ****************************************************************************************************/ |
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517 |
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518 // This transmission enables the tapreg. |
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519 ABB_WriteRegister(TAPCTRL, 0x01); |
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520 |
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521 // This transmission select ABB test instruction. |
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522 ABB_WriteRegister(TAPREG, TSPEN); |
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523 |
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524 // This transmission changes the register page in ABB for usp to pg0. |
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525 ABB_SetPage(PAGE0); |
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526 |
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527 // This transmission enables selected ABB modules. |
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528 ABB_WriteRegister(TOGBR1, modules >> 6); |
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529 |
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530 // enable MB & BB resistive bridges for measurements |
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531 if(modules & MADC) // check if the ADC is enabled |
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532 { |
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533 // This transmission connects the resistive divider to MB and BB. |
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534 ABB_WriteRegister(BCICTL1, 0x0001); |
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535 } |
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536 |
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537 /********* Sleep definition part ******************/ |
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538 // This transmission changes the register page in the ABB for usp to pg1. |
154
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539 #if (ANALOG == 2) |
148
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540 ABB_SetPage(PAGE1); |
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541 |
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542 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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543 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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544 |
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545 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); |
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546 |
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547 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. |
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548 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; |
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549 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); |
154
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550 #elif (ANALOG == 3) |
148
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551 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); |
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552 #endif |
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553 // This transmission changes the register page in the ABB for usp to pg0. |
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554 ABB_SetPage(PAGE0); |
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555 #endif |
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556 |
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557 // SW workaround for initialization of the audio parts of the ABB to avoid white noise |
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558 // C.f. BUG1941 |
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559 // Set VDLR and VULR bits |
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560 // Write TOGBR1 register |
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561 // This transmission enables selected ABB modules. |
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562 ABB_WriteRegister(TOGBR1, 0x0A); |
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563 |
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564 // wait for 1 ms |
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565 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); |
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566 |
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567 // Reset VDLS and VULS bits |
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568 // Write TOGBR1 register |
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569 // This transmission enables selected ABB modules. |
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570 ABB_WriteRegister(TOGBR1, 0x05); |
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571 |
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572 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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573 // release the semaphore only if it has correctly been created. |
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574 if(&abb_sem != 0) |
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575 { |
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576 NU_Release_Semaphore(&abb_sem); |
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577 } |
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|
578 #endif // ABB_SEMAPHORE_PROTECTION |
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|
579 |
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|
580 // Stop the SPI clock |
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|
581 #ifdef SPI_CLK_LOW_POWER |
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|
582 SPI_CLK_DISABLE |
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|
583 #endif |
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|
584 } |
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|
585 |
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|
586 |
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|
587 |
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|
588 /*-----------------------------------------------------------------------*/ |
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|
589 /* ABB_Read_ADC() */ |
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590 /* */ |
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591 /* This function manages all the spi serial transfer to read all the */ |
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592 /* ABB ADC conversion channels. */ |
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593 /* Stores the result in Buff parameter. */ |
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594 /* */ |
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|
595 /*-----------------------------------------------------------------------*/ |
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|
596 void ABB_Read_ADC(SYS_UWORD16 *Buff) |
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|
597 { |
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|
598 volatile SYS_UWORD16 status; |
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|
599 |
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|
600 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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|
601 SPI_Ready_for_RDWR |
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|
602 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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|
603 |
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|
604 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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|
605 |
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|
606 // check if the semaphore has been correctly created and try to obtain it. |
588
1c0033c2fe33
gsm-fw/bsp/abb+spi/abb*.c: formatting fixes (line length and tabs)
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540
diff
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|
607 // if the semaphore cannot be obtained, the task is suspended and then resumed |
148
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|
608 // as soon as the semaphore is released. |
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|
609 if(&abb_sem != 0) |
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|
610 { |
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|
611 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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|
612 } |
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|
613 #endif // ABB_SEMAPHORE_PROTECTION |
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|
614 |
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|
615 // This transmission changes the register page in the ABB for usp to pg0. |
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|
616 ABB_SetPage(PAGE0); |
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|
617 |
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|
618 /* Read all ABB ADC registers */ |
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|
619 *Buff++ = ABB_ReadRegister(VBATREG); |
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|
620 *Buff++ = ABB_ReadRegister(VCHGREG); |
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621 *Buff++ = ABB_ReadRegister(ICHGREG); |
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622 *Buff++ = ABB_ReadRegister(VBKPREG); |
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623 *Buff++ = ABB_ReadRegister(ADIN1REG); |
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624 *Buff++ = ABB_ReadRegister(ADIN2REG); |
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625 *Buff++ = ABB_ReadRegister(ADIN3REG); |
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626 |
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627 #if (ANALOG ==1) |
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628 *Buff++ = ABB_ReadRegister(ADIN4XREG); |
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629 *Buff++ = ABB_ReadRegister(ADIN5YREG); |
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630 #elif (ANALOG ==2) |
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631 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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632 #elif (ANALOG == 3) |
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633 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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634 *Buff++ = ABB_ReadRegister(ADIN5REG); |
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635 #endif // ANALOG |
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636 |
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637 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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638 // release the semaphore only if it has correctly been created. |
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639 if(&abb_sem != 0) |
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640 { |
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641 NU_Release_Semaphore(&abb_sem); |
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642 } |
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643 #endif // ABB_SEMAPHORE_PROTECTION |
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644 |
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645 // Stop the SPI clock |
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646 #ifdef SPI_CLK_LOW_POWER |
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647 SPI_CLK_DISABLE |
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648 #endif |
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649 } |
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650 |
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651 |
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652 |
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653 /*-----------------------------------------------------------------------*/ |
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654 /* ABB_Conf_ADC() */ |
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655 /* */ |
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656 /* This function manages all the spi serial transfer to: */ |
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657 /* - select the ABB ADC channels to be converted */ |
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658 /* - enable/disable EOC interrupt */ |
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659 /* */ |
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660 /*-----------------------------------------------------------------------*/ |
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661 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) |
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662 { |
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663 volatile SYS_UWORD16 status; |
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664 SYS_UWORD16 reg_val; |
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665 |
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666 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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667 SPI_Ready_for_RDWR |
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668 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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669 |
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670 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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671 |
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672 // check if the semaphore has been correctly created and try to obtain it. |
588
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673 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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674 // as soon as the semaphore is released. |
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675 if(&abb_sem != 0) |
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676 { |
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677 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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678 } |
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679 #endif // ABB_SEMAPHORE_PROTECTION |
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680 |
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681 // This transmission changes the register page in the ABB for usp to pg0. |
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682 ABB_SetPage(PAGE0); |
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683 |
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684 /* select ADC channels to be converted */ |
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685 #if (ANALOG == 1) |
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686 ABB_WriteRegister(MADCCTRL1, Channels); |
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687 #elif ((ANALOG == 2) || (ANALOG == 3)) |
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688 ABB_WriteRegister(MADCCTRL, Channels); |
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689 #endif |
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690 |
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691 reg_val = ABB_ReadRegister(ITMASK); |
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692 |
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693 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. |
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694 if(ItVal == EOC_INTENA) |
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695 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); |
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696 else if(ItVal == EOC_INTMASK) |
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697 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); |
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698 |
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699 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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700 // release the semaphore only if it has correctly been created. |
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701 if(&abb_sem != 0) |
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702 { |
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703 NU_Release_Semaphore(&abb_sem); |
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704 } |
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705 #endif // ABB_SEMAPHORE_PROTECTION |
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706 |
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707 // Stop the SPI clock |
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708 #ifdef SPI_CLK_LOW_POWER |
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709 SPI_CLK_DISABLE |
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710 #endif |
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711 } |
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712 |
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|
713 |
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|
714 |
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|
715 |
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716 /*------------------------------------------------------------------------*/ |
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717 /* ABB_sleep() */ |
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718 /* */ |
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719 /* This function disables the DCDC and returns to PAGE 0. It stops then */ |
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720 /* the 13MHz clock in ABB. A wait loop s required to allow */ |
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|
721 /* first slow access to ABB clock register. */ |
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722 /* */ |
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723 /* WARNING !! : this function must not be protected by semaphore !! */ |
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724 /* */ |
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725 /* Returns AFC value. */ |
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726 /* */ |
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727 /*------------------------------------------------------------------------*/ |
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728 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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729 { |
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730 volatile SYS_UWORD16 status; |
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731 SYS_UWORD32 afcout_index; |
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732 volatile SYS_UWORD16 nb_it; |
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733 SYS_UWORD16 reg_val; |
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734 |
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735 // table for AFC allowed values during Sleep mode. First 5th elements |
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736 // are related to positive AFC values, last 5th to negative ones. |
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737 static const SYS_UWORD32 Afcout_T[10] = |
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738 {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; |
148
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739 |
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740 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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741 SPI_Ready_for_RDWR |
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742 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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743 |
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744 // COMPUTATION AND PROGRAMMING OF AFC VALUE |
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745 //--------------------------------------------------- |
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746 if(afc & 0x1000) |
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747 afcout_index = ((afc + 512)>>10) + 1; |
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748 else |
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749 afcout_index = (afc + 512)>>10; |
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750 |
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751 if (sleep_performed == FRAME_STOP) // Big sleep |
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752 { |
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753 #if ((ANALOG == 2) || (ANALOG == 3)) |
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754 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// |
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755 #endif |
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756 |
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757 } |
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758 else // Deep sleep |
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759 { |
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760 #if(ANALOG == 1) |
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761 // SELECTION OF AFC TEST MODE FOR OMEGA |
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762 //--------------------------------------------------- |
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763 // This test configuration allows access on the AFCOUT register |
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764 ABB_SetPage(PAGE1); |
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765 |
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766 // This transmission enables OMEGA test register. |
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767 ABB_WriteRegister(TAPCTRL, 0x01); |
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768 |
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769 // This transmission selects OMEGA test instruction. |
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770 ABB_WriteRegister(TAPREG, AFCTEST); |
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771 |
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772 // Set AFCOUT to 0. |
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773 ABB_WriteRegister(AFCOUT, 0x00 >> 6); |
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774 |
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775 ABB_SetPage(PAGE0); |
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776 |
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777 #elif (ANALOG == 2) |
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778 // This configuration allows access on the AFCOUT register |
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779 ABB_SetPage(PAGE1); |
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780 |
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781 // Read AFCCTLADD value and enable USP access to AFCOUT register |
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782 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); |
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783 |
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784 ABB_WriteRegister(AFCCTLADD, reg_val); |
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785 |
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786 // Set AFCOUT to 0. |
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787 ABB_WriteRegister(AFCOUT, 0x00); |
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788 |
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789 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. |
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790 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; |
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791 |
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792 ABB_WriteRegister(BCICONF, reg_val); |
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793 |
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794 // Disable the ABB test mode |
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795 ABB_WriteRegister(TAPCTRL, 0x00); |
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796 |
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797 ABB_SetPage(PAGE0); |
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798 |
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799 // Read BCICTL1 value and cut the measurement bridge of MB. |
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800 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; |
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801 |
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802 ABB_WriteRegister(BCICTL1, reg_val); |
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803 #endif |
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804 |
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805 #if (ANALOG == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected |
148
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806 // in Syren during sleep mode. BB charge stays enabled |
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807 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission |
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808 // change the register page in IOTA for usp to pg1 |
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809 |
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810 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode |
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811 |
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812 ABB_SetPage(PAGE0); |
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813 #endif |
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814 |
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815 // switch off MADC, AFC, AUXDAC, VOICE. |
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816 ABB_WriteRegister(TOGBR1, 0x155); |
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817 |
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818 // Switch off Analog supply LDO |
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819 //----------------------------- |
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820 #if (ANALOG == 1) |
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821 ABB_SetPage(PAGE1); |
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822 |
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823 // Read VRPCCTL3 register value and switch off VR3. |
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824 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; |
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825 |
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826 ABB_WriteRegister(VRPCCTRL3, reg_val); |
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827 |
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828 #elif (ANALOG == 2) |
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829 // Read VRPCSTS register value and extract status of meaningfull inputs. |
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830 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; |
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831 |
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832 if (reg_val == 0x30) |
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833 { |
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834 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. |
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835 ABB_WriteRegister(VRPCDEV, 0x02); |
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836 } |
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837 |
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838 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". |
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839 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
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840 |
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841 #elif (ANALOG == 3) |
148
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842 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed |
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843 // start the SLPDLY counter in order to switch the ABB in sleep mode |
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844 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission |
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845 // set Syren sleep bit |
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846 /* |
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847 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". |
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848 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
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849 */ |
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850 #endif |
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851 |
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852 // Switch to low frequency clock |
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853 ABB_stop_13M(); |
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854 } |
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855 |
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856 // Stop the SPI clock |
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857 #ifdef SPI_CLK_LOW_POWER |
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858 SPI_CLK_DISABLE |
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859 #endif |
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860 |
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861 #if (OP_L1_STANDALONE == 1) |
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862 #if (CHIPSET == 12) |
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863 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull |
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864 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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865 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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866 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0 |
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867 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode |
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868 #endif |
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869 #endif |
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870 return(Afcout_T[afcout_index]); |
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871 } |
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872 |
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873 |
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874 /*------------------------------------------------------------------------*/ |
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875 /* ABB_wakeup() */ |
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876 /* */ |
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877 /* This function sets the 13MHz clock working in ABB. A wait loop */ |
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878 /* is required to allow first slow access to ABB clock register. */ |
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879 /* Then it re-enables DCDC and returns to PAGE 0. */ |
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880 /* */ |
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881 /* WARNING !! : this function must not be protected by semaphore !! */ |
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882 /* */ |
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883 /*------------------------------------------------------------------------*/ |
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884 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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885 { |
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886 volatile SYS_UWORD16 status; |
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887 SYS_UWORD16 reg_val; |
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888 |
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889 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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890 SPI_Ready_for_RDWR |
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891 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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892 |
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893 if (sleep_performed == FRAME_STOP) // Big sleep |
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894 { |
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895 #if ((ANALOG == 2) || (ANALOG == 3)) |
148
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896 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// |
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897 #endif |
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898 } |
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899 else // Deep sleep |
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900 { |
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901 #if (OP_L1_STANDALONE == 1) |
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902 #if (CHIPSET == 12) |
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903 // restore context from |
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904 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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905 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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906 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 |
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907 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode |
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908 #endif |
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909 #endif |
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|
910 |
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911 // Restitutes 13MHZ Clock to ABB |
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912 ABB_free_13M(); |
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913 |
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914 // Switch ON Analog supply LDO |
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915 #if (ANALOG == 1) |
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916 ABB_SetPage(PAGE1); |
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917 |
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918 // Read VRPCCTL3 register value and switch on VR3. |
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919 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; |
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920 |
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|
921 ABB_WriteRegister(VRPCCTRL3, reg_val); |
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922 ABB_SetPage(PAGE0); |
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923 #endif |
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924 |
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925 // This transmission switches on MADC, AFC. |
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|
926 ABB_WriteRegister(TOGBR1, 0x280); |
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|
927 |
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|
928 // This transmission sets the AUXAFC2. |
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|
929 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); |
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|
930 |
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|
931 // This transmission sets the AUXAFC1. |
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932 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); |
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933 |
154
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934 #if (ANALOG == 1) |
148
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935 // Remove AFC test mode |
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936 ABB_SetPage(PAGE1); |
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937 |
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938 // This transmission select Omega test instruction. |
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939 ABB_WriteRegister(TAPREG, TSPTEST1); |
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940 |
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941 // Disable test mode selection |
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942 // This transmission disables Omega test register. |
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943 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); |
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944 |
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945 ABB_SetPage(PAGE0); |
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946 |
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947 #elif (ANALOG == 2) |
148
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948 ABB_SetPage(PAGE1); |
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949 |
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950 // Read AFCCTLADD register value and disable USP access to AFCOUT register. |
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951 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; |
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952 |
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953 ABB_WriteRegister(AFCCTLADD, reg_val); |
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954 |
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955 // Read BCICONF register value and enable BB measurement bridge enable BB charge. |
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956 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; |
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957 |
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958 ABB_WriteRegister(BCICONF, reg_val); |
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959 |
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960 |
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961 /* *************************************************************************************************** */ |
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962 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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963 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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964 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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965 |
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966 // Enable the ABB test mode |
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967 ABB_WriteRegister(TAPCTRL, 0x01); |
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968 ABB_WriteRegister(TAPREG, TSPEN); |
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969 ABB_SetPage(PAGE0); |
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970 |
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971 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. |
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972 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; |
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973 |
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974 ABB_WriteRegister(BCICTL1, reg_val); |
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975 #endif |
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976 |
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977 #if (ANALOG == 3) |
148
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978 |
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979 ABB_SetPage(PAGE1); |
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980 |
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981 /* *************************************************************************************************** */ |
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982 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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983 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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984 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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985 |
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986 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ |
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987 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
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988 /* ****************************************************************************************************/ |
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989 |
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990 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register |
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991 // This transmission enables IOTA test register |
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992 |
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993 ABB_WriteRegister(TAPREG, TSPEN); |
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994 // This transmission select IOTA test instruction |
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995 // This transmission select IOTA test instruction |
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996 /**************************************************************************************************** */ |
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997 |
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998 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission |
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999 #endif |
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1000 } |
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1001 |
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1002 // Stop the SPI clock |
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1003 #ifdef SPI_CLK_LOW_POWER |
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1004 SPI_CLK_DISABLE |
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1005 #endif |
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1006 } |
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1007 |
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1008 /*------------------------------------------------------------------------*/ |
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1009 /* ABB_wa_VRPC() */ |
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1010 /* */ |
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1011 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ |
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1012 /* according to the ABB used. */ |
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1013 /* */ |
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1014 /*------------------------------------------------------------------------*/ |
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1015 void ABB_wa_VRPC(SYS_UWORD16 value) |
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1016 { |
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1017 volatile SYS_UWORD16 status; |
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1018 |
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1019 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1020 SPI_Ready_for_WR |
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1021 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1022 |
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1023 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1024 |
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1025 // check if the semaphore has been correctly created and try to obtain it. |
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1026 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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1027 // as soon as the semaphore is released. |
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1028 if(&abb_sem != 0) |
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1029 { |
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1030 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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1031 } |
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1032 #endif // ABB_SEMAPHORE_PROTECTION |
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1033 |
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1034 ABB_SetPage(PAGE1); |
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1035 |
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1036 #if (ANALOG == 1) |
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1037 // This transmission initializes the VRPCCTL1 register. |
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1038 ABB_WriteRegister(VRPCCTRL1, value); |
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1039 |
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1040 #elif (ANALOG == 2) |
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1041 // This transmission initializes the VRPCSIM register. |
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1042 ABB_WriteRegister(VRPCSIM, value); |
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1043 |
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1044 #elif (ANALOG == 3) |
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1045 // This transmission initializes the VRPCSIMR register. |
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1046 ABB_WriteRegister(VRPCSIMR, value); |
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1047 |
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1048 #endif |
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1049 |
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1050 ABB_SetPage(PAGE0); |
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1051 |
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1052 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1053 // release the semaphore only if it has correctly been created. |
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1054 if(&abb_sem != 0) |
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1055 { |
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1056 NU_Release_Semaphore(&abb_sem); |
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1057 } |
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1058 #endif // ABB_SEMAPHORE_PROTECTION |
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1059 |
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1060 // Stop the SPI clock |
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1061 #ifdef SPI_CLK_LOW_POWER |
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1062 SPI_CLK_DISABLE |
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1063 #endif |
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1064 } |
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1065 |
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1066 |
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1067 /*-----------------------------------------------------------------------*/ |
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1068 /* ABB_Write_Uplink_Data() */ |
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1069 /* */ |
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1070 /* This function uses the SPI to write to ABB uplink buffer. */ |
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1071 /* */ |
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1072 /*-----------------------------------------------------------------------*/ |
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1073 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) |
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1074 { |
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1075 SYS_UWORD8 i; |
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1076 volatile SYS_UWORD16 status; |
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1077 |
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1078 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1079 SPI_Ready_for_WR |
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1080 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1081 |
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1082 // Select Page 0 for TOGBR2 |
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1083 ABB_SetPage(PAGE0); |
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1084 |
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1085 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 |
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1086 ABB_WriteRegister(TOGBR2, 0x10); |
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1087 |
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1088 // Clear, assuming that it works like IBUFPTR of Vega |
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1089 ABB_WriteRegister(TOGBR2, 0x0); |
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1090 |
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1091 // Write the ramp data |
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1092 for (i=0;i<16;i++) |
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1093 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); |
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1094 |
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1095 // Stop the SPI clock |
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1096 #ifdef SPI_CLK_LOW_POWER |
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1097 SPI_CLK_DISABLE |
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1098 #endif |
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1099 } |
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1100 |
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1101 //////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// |
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1102 |
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1103 #if (ANALOG == 3) |
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1104 |
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1105 // Syren Sleep configuration function -------------------------- |
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1106 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) |
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1107 { |
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1108 volatile SYS_UWORD16 status,sl_ldo_stat; |
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1109 |
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1110 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission |
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1111 // change the register page in ABB for usp to pg1 |
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1112 |
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1113 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value |
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1114 |
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1115 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); |
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1116 |
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1117 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration |
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1118 |
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1119 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission |
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1120 // change the register page in ABB for usp to pg0 |
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1121 } |
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1122 #endif |
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1123 |
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1124 |
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1125 #if (OP_L1_STANDALONE == 0) |
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1126 /*-----------------------------------------------------------------------*/ |
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1127 /* ABB_Power_Off() */ |
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1128 /* */ |
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1129 /* This function uses the SPI to switch off the ABB. */ |
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1130 /* */ |
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1131 /*-----------------------------------------------------------------------*/ |
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1132 void ABB_Power_Off(void) |
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1133 { |
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1134 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). |
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1135 NU_Sleep (30); |
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1136 |
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1137 // Wait also until <ON/OFF> key is released. |
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1138 // This is needed to avoid, if the power key is pressed for a long time, to switch |
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1139 // ON-switch OFF the mobile, until the power key is released. |
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1140 #if((ANALOG == 1) || (ANALOG == 2)) |
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1141 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { |
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1142 #elif(ANALOG == 3) |
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1143 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { |
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1144 #endif |
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1145 |
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1146 NU_Sleep (1); } |
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1147 |
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1148 #if 0 // FreeCalypso |
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1149 BZ_KeyBeep_OFF(); |
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1150 #endif |
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1151 |
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1152 #if(ANALOG == 1) |
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1153 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); |
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1154 #elif((ANALOG == 2) || (ANALOG == 3)) |
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1155 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); |
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1156 #endif |
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1157 } |
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1158 #endif |