FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/cust0/l1_rf2.h @ 509:a92cf1059894
osx.c: _osx_config() done, module complete
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Tue, 01 Jul 2014 20:02:04 +0000 |
parents | 26472940e5b0 |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * |
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4 * Filename l1_rf2.h |
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5 * Copyright 2003 (C) Texas Instruments |
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6 * |
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7 ************* Revision Controle System Header *************/ |
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8 |
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9 #ifndef __L1_RF_H__ |
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10 #define __L1_RF_H__ |
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11 |
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12 /************************************/ |
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13 /************************************/ |
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14 // # define |
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15 /************************************/ |
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16 /************************************/ |
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17 /* SYNTHESIZER setup time... */ |
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18 /************************************/ |
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19 |
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20 #define RX_SYNTH_SETUP_TIME 215L // Synthesizer setup time in quarter bit. |
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21 #define TX_SYNTH_SETUP_TIME 270L // Synthesizer setup time in quarter bit. |
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22 |
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23 /************************************/ |
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24 /* time for TPU scenario ending... */ |
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25 /************************************/ |
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26 |
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27 #define RX_TPU_SCENARIO_ENDING (4-3) // execution time of BDLENA down |
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28 // minus serialization time |
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29 #define TX_TPU_SCENARIO_ENDING (4-3) // execution time of BULON down |
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30 // minus serialization time |
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31 |
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32 /************************************/ |
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33 /* TXPWR configuration... */ |
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34 /************************************/ |
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35 |
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36 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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37 #define FIXED_TXPWR ((0x1FF << 6) | AUXAPC | FALSE) // TXPWR=15 |
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38 // #define FIXED_TXPWR ((0xFF << 6) | AUXAPC | FALSE) |
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39 #endif |
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40 |
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41 /************************************/ |
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42 /* TX Propagation delay... */ |
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43 /************************************/ |
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44 |
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45 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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46 // #define PRG_TX ( 52L ) |
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47 #define PRG_TX ( 8L) |
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48 #endif |
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49 |
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50 /************************************/ |
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51 /*(ANALOG)delay (in qbits) */ |
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52 /************************************/ |
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53 |
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54 #define UL_ABB_DELAY 0 // modulator input to output delay |
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55 |
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56 /************************************/ |
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57 /* Initial value for AFC... */ |
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58 /************************************/ |
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59 |
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60 #define EEPROM_AFC ((-952-2400)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced) |
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61 |
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62 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF Band Gap(in Frames) |
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63 // !! minimum Value : 1 Frame due to the fact there is no |
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64 // hisr() in the first wake-up frame !!!! |
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65 |
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66 #if (ANALOG == 1) |
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67 /************************************/ |
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68 /* Omega power on... */ |
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69 /************************************/ |
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70 // Omega registers values will be programmed at 1st DSP communication interrupt |
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71 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG |
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72 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset |
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73 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB |
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74 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB |
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75 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset |
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76 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) |
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77 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset |
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78 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset |
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79 #define C_DAI_ON_OFF 0x0000 // value at reset |
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80 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset |
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81 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=0, VDLAUX=1, VDLEAR=1 |
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82 |
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83 // BULRUDEL will be initialized on rach only .... |
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84 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | FALSE) |
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85 #endif |
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86 |
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87 #if (ANALOG == 2) |
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88 /************************************/ |
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89 /* Iota power on... */ |
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90 /************************************/ |
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91 // Iota registers values will be programmed at 1st DSP communication interrupt |
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92 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG |
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93 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset |
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94 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB |
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95 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB |
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96 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset |
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97 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB |
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98 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset |
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99 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset |
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100 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset |
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101 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset |
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102 #define C_DAI_ON_OFF 0x0000 // value at reset |
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103 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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104 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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105 |
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106 // BULRUDEL will be initialized on rach only .... |
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107 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE ) |
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108 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) |
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109 #endif |
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110 |
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111 #if (ANALOG == 3) |
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112 // SYREN registers values will be programmed at 1st DSP communication interrupt |
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113 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG |
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114 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset |
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115 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB |
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116 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB |
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117 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V |
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118 // Monoslot, Vpp=8/15*Vref |
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119 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB |
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120 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset |
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121 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset |
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122 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset |
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123 #define C_DAI_ON_OFF 0x0000 // value at reset |
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124 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset |
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125 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB |
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126 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB |
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127 |
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128 // BULRUDEL will be initialized on rach only .... |
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129 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE ) |
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130 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) |
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131 |
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132 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only |
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133 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames |
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134 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero |
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135 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs |
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136 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero |
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137 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero |
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138 |
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139 // SYREN registers values programmed by L1 directly through SPI (ABB_on) |
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140 |
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141 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF |
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142 |
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143 #endif |
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144 |
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145 /************************************/ |
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146 /* Automatic frequency compensation */ |
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147 /************************************/ |
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148 |
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149 /********************* C_Psi_sta definition *****************************/ |
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150 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */ |
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151 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */ |
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152 /* regarding Vega V/N = 2.4/4096 */ |
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153 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */ |
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154 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */ |
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155 /* = 0.000195748 */ |
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156 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */ |
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157 /************************************************************************/ |
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158 |
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159 #define C_Psi_sta_inv 9307L // (1/C_Psi_sta) |
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160 #define C_Psi_st 6 // C_Psi_sta * 0.8 F0.16 |
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161 #define C_Psi_st_32 369173L // F0.32 |
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162 #define C_Psi_st_inv 11634L // (1/C_Psi_st) |
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163 |
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164 typedef struct |
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165 { |
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166 WORD16 eeprom_afc; |
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167 UWORD32 psi_sta_inv; |
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168 UWORD32 psi_st; |
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169 UWORD32 psi_st_32; |
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170 UWORD32 psi_st_inv; |
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171 } |
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172 T_AFC_PARAMS; |
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173 |
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174 /************************************/ |
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175 /* Swap IQ definitions... */ |
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176 /************************************/ |
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177 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */ |
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178 |
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179 #define SWAP_IQ_GSM 0 |
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180 #define SWAP_IQ_DCS 0 |
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181 #define SWAP_IQ_PCS 0 // not supported by rf2 |
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182 #define SWAP_IQ_GSM850 0 // not supported by rf2 |
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183 |
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184 /************************************/ |
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185 /************************************/ |
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186 // typedef |
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187 /************************************/ |
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188 /************************************/ |
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189 |
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190 /*************************************************************/ |
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191 /* Define structure for apc of TX Power ******/ |
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192 /*************************************************************/ |
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193 typedef struct |
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194 { // pcm-file "rf/tx/level.gsm|dcs" |
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195 UWORD16 apc; // 0..31 |
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196 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE |
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197 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE |
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198 } |
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199 T_TX_LEVEL; |
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200 |
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201 /************************************/ |
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202 /* Automatic Gain Control */ |
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203 /************************************/ |
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204 /* Define structure for sub-band definition of TX Power ******/ |
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205 typedef struct |
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206 { |
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207 UWORD16 upper_bound; // highest physical arfcn of the sub-band |
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208 WORD16 agc_calib; // AGC for each TXPWR |
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209 }T_RF_AGC_BAND; |
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210 |
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211 /************************************/ |
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212 /* Ramp definitions */ |
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213 /************************************/ |
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214 |
152
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215 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
151
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216 typedef struct |
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217 { |
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218 UWORD8 ramp_up [16]; // Ramp-up profile |
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219 UWORD8 ramp_down [16]; // Ramp-down profile |
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220 } |
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221 T_TX_RAMP; |
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222 #endif |
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223 |
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224 |
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225 // RF structure definition |
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226 //======================== |
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227 |
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228 enum RfRevision { |
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229 RF_IGNORE = 0x0000, |
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230 RF_SL2 = 0x1000, |
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231 RF_GAIA_20X = 0x2000, |
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232 RF_GAIA_20A = 0x2001, |
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233 RF_GAIA_20B = 0x2002, |
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234 RF_ATLAS_20B = 0x2020, |
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235 RF_PASCAL_20 = 0x2030 |
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236 }; |
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237 |
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238 // Number of bands supported |
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239 #define GSM_BANDS 2 |
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240 |
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241 #define MULTI_BAND1 0 |
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242 #define MULTI_BAND2 1 |
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243 // RF table sizes |
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244 #define RF_RX_CAL_CHAN_SIZE 9 // number of AGC sub-bands |
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245 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges |
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246 |
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247 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size |
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248 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table |
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249 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size |
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250 #define RF_TX_RAMP_SIZE 15 // number of ramp definitions |
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251 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges |
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252 |
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253 #define AGC_TABLE_SIZE 1 |
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254 |
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255 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table |
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256 |
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257 |
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258 // RX parameters and tables |
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259 //------------------------- |
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260 |
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261 // AGC parameters and tables |
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262 typedef struct |
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263 { |
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264 UWORD16 low_agc_noise_thr; |
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265 UWORD16 high_agc_sat_thr; |
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266 UWORD16 low_agc; |
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267 UWORD16 high_agc; |
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268 UWORD8 il2agc_pwr[121]; |
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269 UWORD8 il2agc_max[121]; |
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270 UWORD8 il2agc_av[121]; |
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271 } |
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272 T_AGC; |
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273 |
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274 // Calibration parameters |
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275 typedef struct |
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276 { |
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277 UWORD16 g_magic; |
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278 UWORD16 lna_att; |
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279 UWORD16 lna_switch_thr_low; |
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280 UWORD16 lna_switch_thr_high; |
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281 } |
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282 T_RX_CAL_PARAMS; |
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283 |
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284 // RX temperature compensation |
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285 typedef struct |
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286 { |
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287 WORD16 temperature; |
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288 WORD16 agc_calib; |
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289 } |
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290 T_RX_TEMP_COMP; |
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291 |
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292 // RF RX structure |
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293 typedef struct |
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294 { |
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295 T_AGC agc; |
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296 } |
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297 T_RF_RX; //common |
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298 |
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299 // RF RX structure |
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300 typedef struct |
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301 { |
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302 T_RX_CAL_PARAMS rx_cal_params; |
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303 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE]; |
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304 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE]; |
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305 } |
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306 T_RF_RX_BAND; |
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307 |
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308 |
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309 // TX parameters and tables |
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310 //------------------------- |
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311 |
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312 // TX temperature compensation |
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313 typedef struct |
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314 { |
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315 WORD16 temperature; |
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316 #if (ORDER2_TX_TEMP_CAL==1) |
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317 WORD16 a; |
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318 WORD16 b; |
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319 WORD16 c; |
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320 #else |
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321 WORD16 apc_calib; |
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322 #endif |
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323 } |
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324 T_TX_TEMP_CAL; |
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325 |
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326 // Ramp up and ramp down delay |
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327 typedef struct |
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328 { |
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329 UWORD16 up; |
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330 UWORD16 down; |
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331 } |
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332 T_RAMP_DELAY; |
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333 |
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334 typedef struct |
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335 { |
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336 UWORD16 arfcn_limit; |
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337 WORD16 chan_cal; |
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338 } |
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339 T_TX_CHAN_CAL; |
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340 |
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341 // RF TX structure |
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342 typedef struct |
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343 { |
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344 T_RAMP_DELAY ramp_delay; |
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345 UWORD8 guard_bits; // number of guard bits needed for ramp up |
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346 UWORD8 prg_tx; |
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347 } |
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348 T_RF_TX; //common |
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349 |
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350 // RF TX structure |
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351 typedef struct |
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352 { |
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353 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE]; |
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354 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS]; |
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355 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE]; |
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356 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE]; |
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357 } |
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358 T_RF_TX_BAND; |
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359 |
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360 // band structure |
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361 typedef struct |
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362 { |
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363 T_RF_RX_BAND rx; |
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364 T_RF_TX_BAND tx; |
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365 UWORD8 swap_iq; |
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366 } |
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367 T_RF_BAND; |
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368 |
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369 // RF structure |
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370 typedef struct |
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371 { |
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372 // common for all bands |
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373 UWORD16 rf_revision; |
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374 UWORD16 radio_band_support; |
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375 T_RF_RX rx; |
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376 T_RF_TX tx; |
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377 T_AFC_PARAMS afc; |
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378 } |
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379 T_RF; |
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380 |
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381 /************************************/ |
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382 /* MADC definitions */ |
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383 /************************************/ |
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384 // Omega: 5 external channels if touch screen not used, 3 otherwise |
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385 enum ADC_INDEX { |
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386 ADC_VBAT, |
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387 ADC_VCHARG, |
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388 ADC_ICHARG, |
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389 ADC_VBACKUP, |
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390 ADC_BATTYP, |
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391 ADC_BATTEMP, |
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392 ADC_RFTEMP, |
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393 ADC_ADC3, |
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394 ADC_ADC4, |
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395 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums |
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396 }; |
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397 |
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398 typedef struct |
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399 { |
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400 WORD16 converted[ADC_INDEX_END]; // converted |
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401 UWORD16 raw[ADC_INDEX_END]; // raw from ADC |
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402 } |
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403 T_ADC; |
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404 |
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405 /************************************/ |
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406 /* MADC calibration */ |
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407 /************************************/ |
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408 typedef struct |
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409 { |
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410 UWORD16 a[ADC_INDEX_END]; |
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411 WORD16 b[ADC_INDEX_END]; |
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412 } |
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413 T_ADCCAL; |
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414 |
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415 // Conversion table: ADC value -> temperature |
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416 typedef struct |
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417 { |
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418 UWORD16 adc; // ADC reading is 10 bits |
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419 WORD16 temp; // temp is in approx. range -30..+80 |
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420 } |
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421 T_TEMP; |
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422 |
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423 typedef struct |
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424 { |
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425 char *name; |
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426 void *addr; |
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427 int size; |
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428 } |
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429 T_CONFIG_FILE; |
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430 |
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431 typedef struct |
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432 { |
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433 char *name; // name of ffs file suffix |
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434 T_RF_BAND *addr; // address to default flash structure |
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435 UWORD16 max_carrier; // max carrier |
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436 UWORD16 max_txpwr; // max tx power |
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437 } |
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438 T_BAND_CONFIG; |
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439 |
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440 typedef struct |
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441 { |
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442 UWORD8 band[GSM_BANDS]; // index to band address |
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443 UWORD8 txpwr_tp; // tx power turning point |
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444 UWORD16 first_arfcn; // first index |
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445 } |
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446 T_STD_CONFIG; |
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447 |
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448 enum GSMBAND_DEF |
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449 { |
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450 BAND_NONE, |
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451 BAND_EGSM900, |
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452 BAND_DCS1800, |
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453 BAND_PCS1900, |
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454 BAND_GSM850, |
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455 // put new bands here |
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456 BAND_GSM900 //last entry |
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457 }; |
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458 |
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459 |
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460 /************************************/ |
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461 /* ABB (Omega) Initialization */ |
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462 /************************************/ |
152
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463 #if ((ANALOG == 1) || (ANALOG == 2)) |
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464 #define ABB_TABLE_SIZE 16 |
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465 #endif |
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466 |
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467 #if (ANALOG == 3) |
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468 #define ABB_TABLE_SIZE 22 |
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469 #endif |
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470 |
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471 // Note that this translation is probably not needed at all. But until L1 is |
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472 // (maybe) changed to simply initialize the ABB from a table of words, we |
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473 // use this to make things more easy-readable. |
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474 #if (ANALOG == 1) |
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475 enum ABB_REGISTERS { |
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476 ABB_AFCCTLADD = 0, |
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477 ABB_VBUCTRL, |
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478 ABB_VBDCTRL, |
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479 ABB_BBCTRL, |
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480 ABB_APCOFF, |
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481 ABB_BULIOFF, |
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482 ABB_BULQOFF, |
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483 ABB_DAI_ON_OFF, |
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484 ABB_AUXDAC, |
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485 ABB_VBCTRL, |
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486 ABB_APCDEL1 |
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487 }; |
152
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488 #elif (ANALOG == 2) |
151
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489 enum ABB_REGISTERS { |
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490 ABB_AFCCTLADD = 0, |
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491 ABB_VBUCTRL, |
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492 ABB_VBDCTRL, |
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493 ABB_BBCTRL, |
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494 ABB_BULGCAL, |
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495 ABB_APCOFF, |
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496 ABB_BULIOFF, |
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497 ABB_BULQOFF, |
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498 ABB_DAI_ON_OFF, |
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499 ABB_AUXDAC, |
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500 ABB_VBCTRL1, |
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501 ABB_VBCTRL2, |
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502 ABB_APCDEL1, |
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503 ABB_APCDEL2 |
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504 }; |
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505 #elif (ANALOG == 3) |
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506 enum ABB_REGISTERS { |
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507 ABB_AFCCTLADD = 0, |
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508 ABB_VBUCTRL, |
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509 ABB_VBDCTRL, |
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510 ABB_BBCTRL, |
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511 ABB_BULGCAL, |
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512 ABB_APCOFF, |
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513 ABB_BULIOFF, |
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514 ABB_BULQOFF, |
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515 ABB_DAI_ON_OFF, |
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516 ABB_AUXDAC, |
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517 ABB_VBCTRL1, |
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518 ABB_VBCTRL2, |
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519 ABB_APCDEL1, |
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520 ABB_APCDEL2, |
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521 ABB_VBPOP, |
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522 ABB_VAUDINITD, |
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523 ABB_VAUDCTRL, |
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524 ABB_VAUOCTRL, |
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525 ABB_VAUSCTRL, |
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526 ABB_VAUDPLL |
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527 }; |
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528 #endif |
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529 #endif |