FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/bsp/Makefile @ 854:acc9e473e93f

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gsm-fw/g23m-aci/aci/ati_bas.c: +CGxx fix in preparation for enabling MokoFFS
author Space Falcon <falcon@ivan.Harhan.ORG>
date Thu, 30 Apr 2015 02:56:40 +0000
parents 1199cdf99c32
children 2768b4339275
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 CC= arm-elf-gcc
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 CFLAGS= -O2 -fno-builtin -mthumb-interwork
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 ASFLAGS=-mthumb-interwork
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
4 LD= arm-elf-ld
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
5
644
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
6 sinclude ../include/config.mk
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
7
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
8 IOBJS= irq_twiddle.o niq32.o
644
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
9 XTOBJS= armio.o clkm.o init_target.o inth.o niq.o timer.o timer1.o timer2.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
10
644
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
11 ifeq (${CONFIG_INCLUDE_SIM},1)
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
12 XTOBJS+=sim.o
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
13 IOBJS+= sim32.o
1199cdf99c32 SIM integration: sim32.c compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 597
diff changeset
14 endif
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
15
130
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 128
diff changeset
16 XOBJS= ${XTOBJS} oldint.o
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 128
diff changeset
17 AOBJS= ${IOBJS} oldint.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
18
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
19 HDRS= armio.h clkm.h dma.h inth.h iq.h mem.h rhea_arm.h sim.h timer.h \
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
20 timer1.h timer2.h ulpd.h
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
21
160
dbfc9ff4e8d2 gsm-fw: starting to compile RTC code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 155
diff changeset
22 SUBDIR= abb+spi rtc
161
98be4841eeb7 gsm-fw: RTC code hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 160
diff changeset
23 SUBDIR_XIPCODE= abb+spi/xipcode.o rtc/xipcode.o
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
24
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
25 all: ${IOBJS} ${XOBJS} ${SUBDIR} iramcode.o xipcode.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
26
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
27 ${AOBJS}: ${HDRS}
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
28
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
29 ${XTOBJS}: %.o : %.c ${HDRS}
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
30 ${CC} ${CFLAGS} -mthumb -c $<
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
31
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
32 iramcode.o: ${IOBJS}
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
33 ${LD} -r -o $@ ${IOBJS}
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
34
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
35 xipcode.o: ${XOBJS} ${SUBDIR}
161
98be4841eeb7 gsm-fw: RTC code hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 160
diff changeset
36 ${LD} -r -o $@ ${XOBJS} ${SUBDIR_XIPCODE}
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
37
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
38 ${SUBDIR}: FRC
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
39 cd $@; ${MAKE} ${MFLAGS}
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
40
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
41 clean:
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
42 rm -f *.[oa] *.out *errs
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
43 for i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
44
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
45 FRC: