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annotate gsm-fw/nucleus/asm_defs.h @ 143:afceeeb2cba1

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Our nuc-fw is destined to become gsm-fw, so I went ahead and did the big hg mv
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Tue, 12 Nov 2013 05:35:48 +0000
parents nuc-fw/nucleus/asm_defs.h@947b1f473960
children 9df7f9c72e17
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1 /*
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2 ************************************************************************
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3 *
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4 * Copyright Mentor Graphics Corporation 2002
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5 * All Rights Reserved.
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6 *
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7 * THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
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8 * THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
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9 * SUBJECT TO LICENSE TERMS.
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10 *
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11 ************************************************************************
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12 ************************************************************************
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13 *
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14 * FILE NAME VERSION
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15 *
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16 * asm_defs.inc Nucleus PLUS\ARM925\Code Composer 1.14.1
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17 *
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18 * COMPONENT
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19 *
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20 * IN - Initialization
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21 *
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22 * DESCRIPTION
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23 *
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24 * This file contains the target processor dependent initialization
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25 * values used in int.s, tct.s, and tmt.s
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26 *
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27 * HISTORY
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28 *
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29 * NAME DATE REMARKS
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30 *
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31 * B. Ronquillo 08-28-2002 Released version 1.13.1
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32 *
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33 ************************************************************************
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34 */
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35
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36 /*
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37 **********************************
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38 * BOARD INITIALIZATION CONSTANTS *
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39 **********************************
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40 * Begin define constants used in low-level initialization.
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41 */
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42
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43 /* CPSR control byte definitions */
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44 #define LOCKOUT 0xC0 /* Interrupt lockout value */
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45 #define LOCK_MSK 0xC0 /* Interrupt lockout mask value */
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46 #define MODE_MASK 0x1F /* Processor Mode Mask */
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47 #define SUP_MODE 0x13 /* Supervisor Mode (SVC) */
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48 #define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */
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49 #define IRQ_MODE_OR_LOCKOUT 0xD2 /* Combined IRQ_MODE OR'ed with */
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50 /* LOCKOUT */
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51 #define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */
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52 #define IRQ_BIT 0x80 /* Interrupt bit of CPSR and SPSR */
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53 #define FIQ_BIT 0x40 /* Interrupt bit of CPSR and SPSR */
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54 #define IRQ_BIT_OR_FIQ_BIT 0xC0 /* IRQ or FIQ interrupt bit of CPSR */
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55 /* and SPSR */
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56
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57 /*
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58 ********************************************
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59 * TC_TCB and TC_HCB STRUCT OFFSET DEFINES *
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60 ********************************************
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61 */
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62 #define TC_CREATED 0x00 /* Node for linking to created task */
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63 /* list */
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64 #define TC_ID 0x0C /* Internal TCB ID */
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65 #define TC_NAME 0x10 /* Task name */
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66 #define TC_STATUS 0x18 /* Task status */
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67 #define TC_DELAYED_SUSPEND 0x19 /* Delayed task suspension */
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68 #define TC_PRIORITY 0x1A /* Task priority */
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69 #define TC_PREEMPTION 0x1B /* Task preemption enable */
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70 #define TC_SCHEDULED 0x1C /* Task scheduled count */
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71 #define TC_CUR_TIME_SLICE 0x20 /* Current time slice */
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72 #define TC_STACK_START 0x24 /* Stack starting address */
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73 #define TC_STACK_END 0x28 /* Stack ending address */
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74 #define TC_STACK_POINTER 0x2C /* Task stack pointer */
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75 #define TC_STACK_SIZE 0x30 /* Task stack's size */
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76 #define TC_STACK_MINIMUM 0x34 /* Minimum stack size */
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77 #define TC_CURRENT_PROTECT 0x38 /* Current protection */
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78 #define TC_SAVED_STACK_PTR 0x3C /* Previous stack pointer */
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79 #define TC_ACTIVE_NEXT 0x3C /* Next activated HISR */
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80 #define TC_TIME_SLICE 0x40 /* Task time slice value */
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81 #define TC_ACTIVATION_COUNT 0x40 /* Activation counter */
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82 #define TC_HISR_ENTRY 0x44 /* HISR entry function */
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83 #define TC_HISR_SU_MODE 0x58 /* Sup/User mode indicator for HISRs */
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84 #define TC_HISR_MODULE 0x5C /* Module identifier for HISR's */
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85 #define TC_SU_MODE 0xA8 /* Sup/User mode indicator for Tasks */
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86 #define TC_MODULE 0xAC /* Module identifier for Tasks */