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annotate gsm-fw/L1/cust0/l1_rf10.h @ 556:b3549e06db7e

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l1_drive.c compiles: fix for Calypso A5 key setting found in TSM30 source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 04 Aug 2014 05:54:50 +0000
parents 26472940e5b0
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename l1_rf10.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 #ifndef __L1_RF_H__
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10 #define __L1_RF_H__
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11
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12 // is this defined somewhere else?
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13 //#define RF_HW_BAND_EGSM
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14 //#define RF_HW_BAND_DCS
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15
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16 #define RF_HW_BAND_PCS 0x4
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17 #define RF_HW_BAND_DUAL_US 0x80
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18 #define RF_HW_BAND_DUAL_EXT 0x20
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19
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20 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
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21
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22 // L1 RF SW Multiband configuration
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23 //--------------------------
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24
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25 // RF_SW_MULTIBAND_SUPPORT values
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26 #define SINGLE_BAND_900 1
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27 #define SINGLE_BAND_1800 2
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28 #define SINGLE_BAND_850 3
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29 #define SINGLE_BAND_1900 4
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30 #define DUAL_BAND_900_1800 5
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31 #define DUAL_BAND_850_1900 6
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32 #define TRI_BAND_900_1800_1900 7
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33 #define TRI_BAND_850_1900_1800 8
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34 #define QUAD_BAND 9
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35
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36 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
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37 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
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38 // And also match the RF HW support: RF_HW_BAND_SUPPORT
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39 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
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40
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41 // Generate band dependancy options
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42 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
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43 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
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44
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45 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
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46 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
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47 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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48
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49 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
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50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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51
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52 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
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53 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
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54 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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55 /************************************/
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56 /* SYNTHESIZER setup time... */
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57 /************************************/
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58
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59 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) // RX Synthesizer setup time in qbit.
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60 #define TX_SYNTH_SETUP_TIME (- TRF_T1) // TX Synthesizer setup time in qbit.
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61
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62 /************************************/
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63 /* time for TPU scenario ending... */
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64 /************************************/
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65
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66 #define RX_TPU_SCENARIO_ENDING 0 // execution time of BDLENA down
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67 // contained in serialization time
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68 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 + 1 // execution time of BULON down
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69 // minus serialization time + 1 TPU_MOVE
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70
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71 /******************************************************/
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72 /* TXPWR configuration... */
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73 /* Fixed TXPWR value when GSM management is disabled. */
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74 /******************************************************/
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75
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76 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
151
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77 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
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78 // #define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
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79 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
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80 #endif
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81
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82 /************************************/
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83 /*(ANALOG)delay (in qbits) */
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84 /************************************/
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85 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
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86 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
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87 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
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88
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89 #if (ANALOG == 1)
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90 #define UL_ABB_DELAY 6 // modulator input to output delay
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91 #endif
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92
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93 #if ((ANALOG == 2) || (ANALOG == 3))
151
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94 #define UL_ABB_DELAY 3 // modulator input to output delay
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95 #endif
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96
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97 /************************************/
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98 /* TX Propagation delay... */
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99 /************************************/
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100 #if (ANALOG == 1)
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101 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
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102 #endif
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103
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104 #if (ANALOG == 2) || (ANALOG == 3)
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105 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42
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106 #endif
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107
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108 /************************************/
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109 /* Initial value for APC DELAY */
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110 /************************************/
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111
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112 #if (ANALOG == 1)
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113 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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114 #define APCDEL_DOWN 2 // minimum value: 2
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115 #define APCDEL_UP (6+5) // minimum value: 6
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116 #endif
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117
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118 #if (ANALOG == 2) || (ANALOG == 3)
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119 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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120 #define APCDEL_DOWN (2+0) // minimum value: 2
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121 #define APCDEL_UP (6+8) // minimum value: 6
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122 #endif
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123
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124 #define GUARD_BITS 8
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125
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126 /************************************/
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127 /* Initial value for AFC... */
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128 /************************************/
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129
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130 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
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131
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132 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames
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133 // Clara (RF=10) LDO wakeup requires 3 frames
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134
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135 /************************************/
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136 /* Baseband registers */
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137 /************************************/
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138
152
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139 #if (ANALOG == 1)
151
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140
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141 // Omega registers values will be programmed at 1st DSP communication interrupt
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142
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143 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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145 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
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146 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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147 #define C_APCOFF ((0x07c << 6) | APCOFF | TRUE ) // value at reset-Changed from 0x0016- CR 27.12
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148 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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149 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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150 #define C_DAI_ON_OFF (0x000) // value at reset
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151 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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152 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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153
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154 // BULRUDEL will be initialized on rach only ....
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155 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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156 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
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157 #endif
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158
152
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159 #if (ANALOG == 2)
151
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160
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161 // IOTA registers values will be programmed at 1st DSP communication interrupt
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162
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163 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
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164 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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165 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
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166 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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167 #define C_APCOFF ((0x068 << 6) | APCOFF | TRUE ) // value at reset-Changed from 3c to 28 CR 17.11.02// x2 slope 128
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168 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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169 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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170 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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171 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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172 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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173 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
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174
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175 // BULRUDEL will be initialized on rach only ....
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176 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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177 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) //
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178
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179 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External RX I/Q DC offset calibration, Output common mode=1.35V
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180 // Monoslot, Vpp=8/15*Vref
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181 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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182 #endif
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183
152
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184 #if (ANALOG == 3)
151
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185
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186 // SYREN registers values will be programmed at 1st DSP communication interrupt
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187
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188 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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189 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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190 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3 dB
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191 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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192 #define C_APCOFF ((0x07c << 6) | APCOFF | TRUE ) // value at reset-Changed from 0x0016- CR 27.12
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193 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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194 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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195 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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196 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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197 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
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198 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
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199
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200 // BULRUDEL will be initialized on rach only ....
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201 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
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202 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
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203
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204 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External autocalibration, Output common mode=1.35V
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205 // Monoslot, Vpp=8/15*Vref
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206 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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207
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208 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
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209 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
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210 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
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211 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
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212 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
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213 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
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214
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215 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
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216
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217 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
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218
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219 #endif
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220
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221 /************************************/
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222 /* Automatic frequency compensation */
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223 /************************************/
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224 /********************* C_Psi_sta definition *****************************/
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225 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
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226 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
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227 /* regarding Vega V/N = 2.4/4096 */
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228 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
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229 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
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230 /* = 0.000195748 */
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231 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
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232 /************************************************************************/
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233
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234 #define C_Psi_sta_inv 4174L // (1/C_Psi_sta)
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235 #define C_Psi_st 13L // C_Psi_sta * 0.8 F0.16
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236 #define C_Psi_st_32 823216L // F0.32
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237 #define C_Psi_st_inv 5217L // (1/C_Psi_st)
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238
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239 #if (VCXO_ALGO == 1)
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240 // Linearity parameters
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241 #define C_AFC_DAC_CENTER ((111)*8)
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242 #define C_AFC_DAC_MIN ((-1196)*8)
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243 #define C_AFC_DAC_MAX ((1419)*8)
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244
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245 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
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246 #endif
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247
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248 typedef struct
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249 {
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250 WORD16 eeprom_afc;
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251 UWORD32 psi_sta_inv;
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252 UWORD32 psi_st;
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253 UWORD32 psi_st_32;
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254 UWORD32 psi_st_inv;
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255
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256 #if (VCXO_ALGO == 1)
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257 // VCXO adjustment parameters
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258 // Parameters used when assuming linearity
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259 WORD16 dac_center;
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260 WORD16 dac_min;
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261 WORD16 dac_max;
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262 WORD16 snr_thr;
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263 #endif
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264 }
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265 T_AFC_PARAMS;
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266
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267 /************************************/
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268 /* Swap IQ definitions... */
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269 /************************************/
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270 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
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271
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272 #define SWAP_IQ_GSM 0
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273 #define SWAP_IQ_DCS 2 // was 2 for sara version 1
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274 #define SWAP_IQ_PCS 2
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275 #define SWAP_IQ_GSM850 0 // TBD
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276
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277 /************************************/
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278 /************************************/
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279 // typedef
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280 /************************************/
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281 /************************************/
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282
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283 /*************************************************************/
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284 /* Define structure for apc of TX Power ******/
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285 /*************************************************************/
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286
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287 typedef struct
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288 { // pcm-file "rf/tx/level.gsm|dcs"
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289 UWORD16 apc; // 0..31
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290 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
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291 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
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292 }
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293 T_TX_LEVEL;
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294
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295 /************************************/
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296 /* Automatic Gain Control */
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297 /************************************/
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298 /* Define structure for sub-band definition of TX Power ******/
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299 typedef struct
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300 {
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301 UWORD16 upper_bound; // highest physical arfcn of the sub-band
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302 WORD16 agc_calib; // AGC for each TXPWR
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303 }T_RF_AGC_BAND;
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304
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305 /************************************/
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306 /* Ramp definitions */
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307 /************************************/
152
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308 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
151
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309 typedef struct
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310 {
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311 UWORD8 ramp_up [16]; // Ramp-up profile
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312 UWORD8 ramp_down [16]; // Ramp-down profile
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313 }
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314 T_TX_RAMP;
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315 #endif
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316
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317
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318 // RF structure definition
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319 //========================
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320
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321 enum RfRevision {
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322 RF_IGNORE = 0x0000,
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323 RF_SL2 = 0x1000,
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324 RF_GAIA_20X = 0x2000,
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325 RF_GAIA_20A = 0x2001,
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326 RF_GAIA_20B = 0x2002,
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327 RF_ATLAS_20B = 0x2020,
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328 RF_PASCAL_20 = 0x2030
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329 };
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330
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331 // Number of bands supported
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332 #define GSM_BANDS 2
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333
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334 #define MULTI_BAND1 0
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335 #define MULTI_BAND2 1
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336
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337 // RF table sizes
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338 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
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339 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
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340
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341 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
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342 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
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343 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
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344 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
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345 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
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346
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347 #define AGC_TABLE_SIZE 27
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348
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349 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
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350
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351
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352 // RX parameters and tables
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353 //-------------------------
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354
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355 // AGC parameters and tables
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356 typedef struct
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357 {
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358 UWORD16 low_agc_noise_thr;
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359 UWORD16 high_agc_sat_thr;
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360 UWORD16 low_agc;
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361 UWORD16 high_agc;
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362 UWORD8 il2agc_pwr[121];
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363 UWORD8 il2agc_max[121];
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364 UWORD8 il2agc_av[121];
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365 }
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366 T_AGC;
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367
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368 // Calibration parameters
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369 typedef struct
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370 {
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371 UWORD16 g_magic;
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372 UWORD16 lna_att;
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373 UWORD16 lna_switch_thr_low;
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374 UWORD16 lna_switch_thr_high;
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375 }
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376 T_RX_CAL_PARAMS;
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377
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378 // RX temperature compensation
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379 typedef struct
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380 {
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381 WORD16 temperature;
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382 WORD16 agc_calib;
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383 }
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384 T_RX_TEMP_COMP;
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385
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386 // RF RX structure
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387 typedef struct
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388 {
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389 T_AGC agc;
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390 }
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parents:
diff changeset
391 T_RF_RX; //common
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diff changeset
392
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parents:
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393 // RF RX structure
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parents:
diff changeset
394 typedef struct
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parents:
diff changeset
395 {
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396 T_RX_CAL_PARAMS rx_cal_params;
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diff changeset
397 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
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diff changeset
398 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
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parents:
diff changeset
399 }
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diff changeset
400 T_RF_RX_BAND;
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parents:
diff changeset
401
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diff changeset
402
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parents:
diff changeset
403 // TX parameters and tables
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parents:
diff changeset
404 //-------------------------
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diff changeset
405
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diff changeset
406 // TX temperature compensation
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parents:
diff changeset
407 typedef struct
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diff changeset
408 {
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diff changeset
409 WORD16 temperature;
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parents:
diff changeset
410 #if (ORDER2_TX_TEMP_CAL==1)
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parents:
diff changeset
411 WORD16 a;
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diff changeset
412 WORD16 b;
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diff changeset
413 WORD16 c;
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diff changeset
414 #else
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diff changeset
415 WORD16 apc_calib;
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diff changeset
416 #endif
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diff changeset
417 }
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418 T_TX_TEMP_CAL;
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419
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420
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diff changeset
421 // Ramp up and ramp down delay
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parents:
diff changeset
422 typedef struct
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parents:
diff changeset
423 {
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424 UWORD16 up;
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425 UWORD16 down;
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parents:
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426 }
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427 T_RAMP_DELAY;
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428
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429 typedef struct
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diff changeset
430 {
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diff changeset
431 UWORD16 arfcn_limit;
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diff changeset
432 WORD16 chan_cal;
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433 }
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434 T_TX_CHAN_CAL;
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435
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diff changeset
436 // RF TX structure
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diff changeset
437 typedef struct
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diff changeset
438 {
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diff changeset
439 T_RAMP_DELAY ramp_delay;
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parents:
diff changeset
440 UWORD8 guard_bits; // number of guard bits needed for ramp up
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parents:
diff changeset
441 UWORD8 prg_tx;
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diff changeset
442 }
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diff changeset
443 T_RF_TX; //common
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diff changeset
444
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diff changeset
445 // RF TX structure
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parents:
diff changeset
446 typedef struct
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diff changeset
447 {
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diff changeset
448 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
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diff changeset
449 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
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diff changeset
450 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
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diff changeset
451 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
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diff changeset
452 }
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diff changeset
453 T_RF_TX_BAND;
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diff changeset
454
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diff changeset
455 // band structure
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parents:
diff changeset
456 typedef struct
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diff changeset
457 {
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diff changeset
458 T_RF_RX_BAND rx;
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diff changeset
459 T_RF_TX_BAND tx;
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diff changeset
460 UWORD8 swap_iq;
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diff changeset
461 }
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diff changeset
462 T_RF_BAND;
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diff changeset
463
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diff changeset
464 // RF structure
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diff changeset
465 typedef struct
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diff changeset
466 {
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467 // common for all bands
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468 UWORD16 rf_revision;
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diff changeset
469 UWORD16 radio_band_support;
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diff changeset
470 T_RF_RX rx;
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diff changeset
471 T_RF_TX tx;
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diff changeset
472 T_AFC_PARAMS afc;
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diff changeset
473 }
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diff changeset
474 T_RF;
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diff changeset
475
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parents:
diff changeset
476 /************************************/
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parents:
diff changeset
477 /* MADC definitions */
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parents:
diff changeset
478 /************************************/
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diff changeset
479 // Omega: 5 external channels if touch screen not used, 3 otherwise
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parents:
diff changeset
480 enum ADC_INDEX {
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diff changeset
481 ADC_VBAT,
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diff changeset
482 ADC_VCHARG,
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diff changeset
483 ADC_ICHARG,
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diff changeset
484 ADC_VBACKUP,
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diff changeset
485 ADC_BATTYP,
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diff changeset
486 ADC_BATTEMP,
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diff changeset
487 ADC_ADC3, // name of this ??
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diff changeset
488 ADC_RFTEMP,
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diff changeset
489 ADC_ADC4,
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diff changeset
490 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
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diff changeset
491 };
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diff changeset
492
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diff changeset
493 typedef struct
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parents:
diff changeset
494 {
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diff changeset
495 WORD16 converted[ADC_INDEX_END]; // converted
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diff changeset
496 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
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diff changeset
497 }
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diff changeset
498 T_ADC;
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diff changeset
499
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diff changeset
500 /************************************/
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parents:
diff changeset
501 /* MADC calibration */
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parents:
diff changeset
502 /************************************/
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parents:
diff changeset
503 typedef struct
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parents:
diff changeset
504 {
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diff changeset
505 UWORD16 a[ADC_INDEX_END];
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diff changeset
506 WORD16 b[ADC_INDEX_END];
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diff changeset
507 }
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508 T_ADCCAL;
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diff changeset
509
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diff changeset
510 // Conversion table: ADC value -> temperature
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diff changeset
511 typedef struct
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diff changeset
512 {
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diff changeset
513 UWORD16 adc; // ADC reading is 10 bits
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diff changeset
514 WORD16 temp; // temp is in approx. range -30..+80
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diff changeset
515 }
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diff changeset
516 T_TEMP;
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diff changeset
517
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diff changeset
518 typedef struct
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parents:
diff changeset
519 {
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diff changeset
520 char *name;
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diff changeset
521 void *addr;
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diff changeset
522 int size;
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diff changeset
523 }
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diff changeset
524 T_CONFIG_FILE;
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diff changeset
525
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diff changeset
526 typedef struct
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parents:
diff changeset
527 {
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diff changeset
528 char *name; // name of ffs file suffix
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diff changeset
529 T_RF_BAND *addr; // address to default flash structure
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parents:
diff changeset
530 UWORD16 max_carrier; // max carrier
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parents:
diff changeset
531 UWORD16 max_txpwr; // max tx power
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parents:
diff changeset
532 }
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diff changeset
533 T_BAND_CONFIG;
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parents:
diff changeset
534
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diff changeset
535 typedef struct
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parents:
diff changeset
536 {
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diff changeset
537 UWORD8 band[GSM_BANDS]; // index to band address
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
538 UWORD8 txpwr_tp; // tx power turning point
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
539 UWORD16 first_arfcn; // first index
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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540 }
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
541 T_STD_CONFIG;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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542
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
543 enum GSMBAND_DEF
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
544 {
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parents:
diff changeset
545 BAND_NONE,
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parents:
diff changeset
546 BAND_EGSM900,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
547 BAND_DCS1800,
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parents:
diff changeset
548 BAND_PCS1900,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
549 BAND_GSM850,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
550 BAND_PCS1900_US,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
551 // put new bands here
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parents:
diff changeset
552 BAND_GSM900 // last entry
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
553 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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554
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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555 /************************************/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
556 /* ABB (Omega) Initialization */
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
557 /************************************/
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parents:
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558
152
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parents: 151
diff changeset
559 #if ((ANALOG == 1) || (ANALOG == 2))
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
560 #define ABB_TABLE_SIZE 16
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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561 #endif
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parents:
diff changeset
562
152
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parents: 151
diff changeset
563 #if (ANALOG == 3)
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
564 #define ABB_TABLE_SIZE 22
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
565 #endif
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parents:
diff changeset
566
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
567 // Note that this translation is probably not needed at all. But until L1 is
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
568 // (maybe) changed to simply initialize the ABB from a table of words, we
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
569 // use this to make things more easy-readable.
152
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parents: 151
diff changeset
570 #if (ANALOG == 1)
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
571 enum ABB_REGISTERS {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
572 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
573 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
574 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
575 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
576 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
577 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
578 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
579 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
580 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
581 ABB_VBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
582 ABB_APCDEL1
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
583 };
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parents:
diff changeset
584 #endif
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parents:
diff changeset
585
152
26472940e5b0 l1_rf<N>.h headers preened
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parents: 151
diff changeset
586 #if (ANALOG == 2)
151
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parents:
diff changeset
587 enum ABB_REGISTERS {
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parents:
diff changeset
588 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
589 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
590 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
591 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
592 ABB_BULGCAL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
593 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
594 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
595 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
596 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
597 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
598 ABB_VBCTRL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
599 ABB_VBCTRL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
600 ABB_APCDEL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
601 ABB_APCDEL2
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
602 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
603 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
604
152
26472940e5b0 l1_rf<N>.h headers preened
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parents: 151
diff changeset
605 #if (ANALOG == 3)
151
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
606 enum ABB_REGISTERS {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
607 ABB_AFCCTLADD = 0,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
608 ABB_VBUCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
609 ABB_VBDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
610 ABB_BBCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
611 ABB_BULGCAL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
612 ABB_APCOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
613 ABB_BULIOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
614 ABB_BULQOFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
615 ABB_DAI_ON_OFF,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
616 ABB_AUXDAC,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
617 ABB_VBCTRL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
618 ABB_VBCTRL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
619 ABB_APCDEL1,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
620 ABB_APCDEL2,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
621 ABB_VBPOP,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
622 ABB_VAUDINITD,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
623 ABB_VAUDCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
624 ABB_VAUOCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
625 ABB_VAUSCTRL,
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
626 ABB_VAUDPLL
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
627 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
628 #endif
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parents:
diff changeset
629
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
630 #endif
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parents:
diff changeset
631