FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/bsp/Makefile @ 611:bbe2b0d17d1e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gsm-fw/L1/audio_cfile/l1audio_init.c: hack to pass compilation w/o AUDIO_TASK
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 29 Aug 2014 05:44:42 +0000
parents 8be182dd9218
children 1199cdf99c32
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 CC= arm-elf-gcc
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 CFLAGS= -O2 -fno-builtin -mthumb-interwork
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 ASFLAGS=-mthumb-interwork
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
4 LD= arm-elf-ld
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
5
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
6 IOBJS= irq_twiddle.o niq32.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
7
115
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 114
diff changeset
8 XTOBJS= armio.o clkm.o init_target.o inth.o niq.o timer.o timer1.o timer2.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
9
130
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 128
diff changeset
10 XOBJS= ${XTOBJS} oldint.o
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 128
diff changeset
11 AOBJS= ${IOBJS} oldint.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
12
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
13 HDRS= armio.h clkm.h dma.h inth.h iq.h mem.h rhea_arm.h sim.h timer.h \
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
14 timer1.h timer2.h ulpd.h
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
15
160
dbfc9ff4e8d2 gsm-fw: starting to compile RTC code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 155
diff changeset
16 SUBDIR= abb+spi rtc
161
98be4841eeb7 gsm-fw: RTC code hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 160
diff changeset
17 SUBDIR_XIPCODE= abb+spi/xipcode.o rtc/xipcode.o
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
18
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
19 all: ${IOBJS} ${XOBJS} ${SUBDIR} iramcode.o xipcode.o
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
20
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
21 ${AOBJS}: ${HDRS}
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
22
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
23 ${XTOBJS}: %.o : %.c ${HDRS}
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
24 ${CC} ${CFLAGS} -mthumb -c $<
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
25
597
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
26 iramcode.o: ${IOBJS}
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
27 ${LD} -r -o $@ ${IOBJS}
8be182dd9218 gsm-fw: INT_{Dis,En}ableIRQ() functions implemented (needed by L1 code)
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 161
diff changeset
28
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
29 xipcode.o: ${XOBJS} ${SUBDIR}
161
98be4841eeb7 gsm-fw: RTC code hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 160
diff changeset
30 ${LD} -r -o $@ ${XOBJS} ${SUBDIR_XIPCODE}
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
31
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
32 ${SUBDIR}: FRC
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
33 cd $@; ${MAKE} ${MFLAGS}
128
789a9a95533f nuc-fw: more minor preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 115
diff changeset
34
93
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
35 clean:
155
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
36 rm -f *.[oa] *.out *errs
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
37 for i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
38
3be2bc80ad38 gsm-fw/bsp/Makefile: abb+spi hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
39 FRC: