FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/services/ffs/drv.c @ 214:bdfdea886bea
gsm-fw/services/ffs: ffs_env.c and ffstrace.c compile
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Mon, 06 Jan 2014 04:43:21 +0000 |
parents | 6f4a12b4582f |
children | fee45482aa2a |
rev | line source |
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1 /****************************************************************************** |
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2 * Flash File System (ffs) |
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com |
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4 * |
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5 * ffs low level flash driver |
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6 * |
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7 * $Id: drv.c 1.30.1.6.1.51.1.1.1.13.1.11 Tue, 06 Jan 2004 14:36:52 +0100 tsj $ |
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8 * |
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9 ******************************************************************************/ |
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10 |
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11 #include "../../include/config.h" |
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12 #include "ffs.h" |
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13 #include "drv.h" |
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14 #include "ffstrace.h" |
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15 #include "intctl.h" |
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16 #include "ramffs.h" |
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17 #include <string.h> |
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18 |
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19 |
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20 /****************************************************************************** |
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21 * Macros |
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22 ******************************************************************************/ |
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23 |
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24 #define addr2offset(address) ( (int) (address) - (int) dev.base ) |
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25 |
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26 |
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27 /****************************************************************************** |
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28 * Generic Driver Functions |
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29 ******************************************************************************/ |
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30 |
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31 // Note: This function is designed for little-endian memory addressing! |
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32 void ffsdrv_write_byte(void *dst, uint8 value) |
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33 { |
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34 uint16 halfword; |
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35 |
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36 tw(tr(TR_FUNC, TrDrvWrite, "ffsdrv_write_byte(0x%05x, 0x%x)\n", |
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37 (int) (addr2offset(dst)), value)); |
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38 ttw(str(TTrDrvWrite, "wb" NL)); |
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39 |
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40 if ((int) dst & 1) |
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41 halfword = (value << 8) | *((uint8 *) dst - 1); |
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42 else |
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43 halfword = (*((uint8 *) dst + 1) << 8) | (value); |
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44 |
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45 ffsdrv.write_halfword((uint16 *) ((int) dst & ~1), halfword); |
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46 } |
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47 |
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48 void ffsdrv_generic_write(void *dst, const void *src, uint16 size) |
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49 { |
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50 uint8 *mydst = dst; |
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51 const uint8 *mysrc = src; |
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52 |
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53 if (size > 0) |
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54 { |
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55 if ((unsigned int) mydst & 1) { |
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56 ffsdrv_write_byte(mydst++, *mysrc++); |
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57 size--; |
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58 } |
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59 while (size >= 2) { |
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60 ffsdrv.write_halfword((uint16 *) mydst, |
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61 mysrc[0] | (mysrc[1] << 8)); |
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62 size -= 2; |
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63 mysrc += 2; |
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64 mydst += 2; |
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65 } |
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66 if (size == 1) |
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67 ffsdrv_write_byte(mydst++, *mysrc++); |
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68 } |
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69 } |
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70 |
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71 /****************************************************************************** |
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72 * Dummy Functions |
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73 ******************************************************************************/ |
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74 |
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75 int ffsdrv_null_init(void) |
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76 { |
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77 ttw(ttr(TTrDrvOther, "ffsdrv_null_init()" NL)); |
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78 |
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79 return 0; |
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80 } |
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81 |
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82 void ffsdrv_null_erase(uint8 block) |
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83 { |
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84 ttw(ttr(TTrDrvErase, "ffsdrv_null_erase(%d)" NL, block)); |
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85 } |
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86 |
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87 void ffsdrv_null_write_halfword(volatile uint16 *addr, uint16 value) |
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88 { |
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89 ttw(ttr(TTrDrvWrite, "ffsdrv_null_write_halfword(0x%x, 0x%x)" NL, addr, value)); |
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90 } |
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91 |
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92 void ffsdrv_null_write(void *dst, const void *src, uint16 size) |
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93 { |
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94 ttw(ttr(TTrDrvWrite, "ffsdrv_null_write(0x%x, 0x%x, %d)" NL, dst, src, size)); |
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95 } |
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96 |
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97 void ffsdrv_null_erase_suspend(void) |
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98 { |
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99 ttw(str(TTrDrvErase, "ffsdrv_null_erase_suspend()" NL)); |
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100 } |
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101 |
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102 void ffsdrv_null_erase_resume(void) |
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103 { |
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104 ttw(str(TTrDrvErase, "ffsdrv_null_erase_resume()" NL)); |
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105 } |
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106 |
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107 void ffsdrv_null_write_end(void) |
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108 { |
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109 ttw(str(TTrDrvWrite, "ffsdrv_null_write_end()" NL)); |
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110 } |
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111 |
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112 void ffsdrv_null_erase_end(void) |
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113 { |
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114 ttw(str(TTrDrvErase, "ffsdrv_null_erase_end()" NL)); |
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115 } |
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116 |
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117 /* |
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118 * FreeCalypso change from TI: we only compile one flash "driver" type |
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119 * based on the build configuration. |
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120 */ |
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121 |
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122 #if FFS_IN_RAM |
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123 |
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124 /****************************************************************************** |
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125 * RAM Family Functions |
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126 ******************************************************************************/ |
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127 |
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128 struct block_info_s ramffs_block_info[RAMFFS_NBLOCKS]; |
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129 |
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130 int ffsdrv_ram_init(void) |
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131 { |
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132 unsigned i; |
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133 uint32 offset; |
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134 |
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135 ttw(ttr(TTrDrvOther, "ffsdrv_ram_init()" NL)); |
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136 memset(_RAMFFS_area, 0xFF, RAMFFS_TOTAL_SIZE); |
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137 offset = 0; |
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138 for (i = 0; i < RAMFFS_NBLOCKS; i++) { |
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139 ramffs_block_info[i].offset = offset; |
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140 ramffs_block_info[i].size_ld = RAMFFS_BLKSIZE_LOG2; |
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141 offset += RAMFFS_BLKSIZE_BYTES; |
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142 } |
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143 return 0; |
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144 } |
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145 |
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146 void ffsdrv_ram_write_halfword(volatile uint16 *dst, uint16 value) |
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147 { |
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148 *dst = value; |
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149 } |
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150 |
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151 #if 0 |
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152 /* duplicates ffsdrv_generic_write */ |
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153 void ffsdrv_ram_write(void *dst, const void *src, uint16 size) |
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154 { |
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155 uint8 *mydst = dst; |
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156 const uint8 *mysrc = src; |
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157 |
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158 if (size == 0) |
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159 return; |
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160 else if (size == 1) |
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161 ffsdrv_write_byte(mydst, *mysrc); |
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162 else { |
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163 if ((int) mydst & 1) { |
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164 ffsdrv_write_byte(mydst++, *mysrc++); |
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165 size--; |
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166 } |
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167 while (size >= 2) { |
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168 ffsdrv_ram_write_halfword((uint16 *) mydst, mysrc[0]|(mysrc[1] << 8)); |
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169 size -= 2; |
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170 mysrc += 2; |
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171 mydst += 2; |
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172 } |
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173 if (size == 1) |
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174 ffsdrv_write_byte(mydst++, *mysrc++); |
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175 } |
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176 } |
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177 #endif |
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178 |
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179 void ffsdrv_ram_erase(uint8 block) |
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180 { |
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181 int i; |
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182 char *addr; |
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183 |
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184 addr = block2addr(block); |
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185 |
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186 for (i = 0; i < (1 << dev.binfo[block].size_ld); i++) { |
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187 *addr++ = 0xFF; |
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188 } |
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189 } |
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190 |
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191 const struct ffsdrv_s ffsdrv = { |
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192 ffsdrv_ram_init, |
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193 ffsdrv_ram_erase, |
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194 ffsdrv_ram_write_halfword, |
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195 ffsdrv_generic_write, |
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196 ffsdrv_null_write_end, |
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197 ffsdrv_null_erase_suspend, |
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198 ffsdrv_null_erase_resume |
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199 }; |
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200 |
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201 #elif CONFIG_FLASH_WRITE |
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202 |
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203 /****************************************************************************** |
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204 * AMD Dual/Multi Bank Driver Functions |
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205 ******************************************************************************/ |
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206 |
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207 // All erase and write operations are performed atomically (interrupts |
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208 // disabled). Otherwise we cannot trust the value of dev.state and we cannot |
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209 // determine exactly how many of the command words have already been |
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210 // written. |
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211 |
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212 // in ffs_end() when we resume an erasure that was previously suspended, how |
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213 // does that affect multiple tasks doing that simultaneously? |
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214 |
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215 void ffsdrv_amd_write_end(void); |
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216 void ffsdrv_amd_erase_end(void); |
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217 |
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218 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value) |
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219 { |
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220 volatile char *flash = dev.base; |
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221 uint32 cpsr; |
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222 |
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223 tlw(led_on(LED_WRITE)); |
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224 ttw(ttr(TTrDrvWrite, "wh(%x,%x)" NL, addr, value)); |
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225 |
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226 dev.addr = addr; |
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227 dev.data = value; |
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228 |
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229 if (~*addr & value) { |
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230 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value)); |
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231 return; |
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232 } |
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233 |
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234 cpsr = int_disable(); |
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235 tlw(led_toggle(LED_WRITE_SUSPEND)); |
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236 dev.state = DEV_WRITE; |
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237 flash[0xAAAA] = 0xAA; // unlock cycle 1 |
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238 flash[0x5555] = 0x55; // unlock cycle 2 |
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239 flash[0xAAAA] = 0xA0; |
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240 *addr = value; |
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241 int_enable(cpsr); |
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242 tlw(led_toggle(LED_WRITE_SUSPEND)); |
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243 |
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244 ffsdrv_amd_write_end(); |
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245 } |
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246 |
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247 #if 0 |
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248 /* duplicates ffsdrv_generic_write */ |
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249 void ffsdrv_amd_write(void *dst, const void *src, uint16 size) |
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250 { |
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251 uint8 *mydst = dst; |
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252 const uint8 *mysrc = src; |
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253 |
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254 if (size > 0) |
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255 { |
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256 if ((unsigned int) mydst & 1) { |
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257 ffsdrv_write_byte(mydst++, *mysrc++); |
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258 size--; |
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259 } |
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260 while (size >= 2) { |
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261 ffsdrv_amd_write_halfword((uint16 *) mydst, |
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262 mysrc[0] | (mysrc[1] << 8)); |
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263 size -= 2; |
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264 mysrc += 2; |
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265 mydst += 2; |
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266 } |
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267 if (size == 1) |
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268 ffsdrv_write_byte(mydst++, *mysrc++); |
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269 } |
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270 } |
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271 #endif |
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272 |
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273 void ffsdrv_amd_write_end(void) |
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274 { |
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275 while ((*dev.addr ^ dev.data) & 0x80) |
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276 tlw(led_toggle(LED_WRITE_SUSPEND)); |
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277 |
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278 dev.state = DEV_READ; |
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279 |
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280 tlw(led_off(LED_WRITE)); |
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281 } |
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282 |
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283 void ffsdrv_amd_erase(uint8 block) |
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284 { |
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285 volatile char *flash = dev.base; |
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286 uint32 cpsr; |
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287 |
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288 tlw(led_on(LED_ERASE)); |
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289 ttw(ttr(TTrDrvErase, "e(%d)" NL, block)); |
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290 |
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291 dev.addr = (uint16 *) block2addr(block); |
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292 |
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293 cpsr = int_disable(); |
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294 dev.state = DEV_ERASE; |
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295 flash[0xAAAA] = 0xAA; // unlock cycle 1 |
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296 flash[0x5555] = 0x55; // unlock cycle 2 |
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297 flash[0xAAAA] = 0x80; |
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298 flash[0xAAAA] = 0xAA; // unlock cycle 1 |
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299 flash[0x5555] = 0x55; // unlock cycle 2 |
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300 *dev.addr = 0x30; // AMD erase sector command |
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301 int_enable(cpsr); |
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302 |
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303 ffsdrv_amd_erase_end(); |
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304 } |
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305 |
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306 void ffsdrv_amd_erase_end(void) |
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307 { |
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308 while ((*dev.addr & 0x80) == 0) |
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309 ; |
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310 |
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311 dev.state = DEV_READ; |
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312 |
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313 tlw(led_off(LED_ERASE)); |
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314 } |
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315 |
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316 void ffsdrv_amd_erase_suspend(void) |
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317 { |
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318 uint32 cpsr; |
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319 |
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320 tlw(led_on(LED_ERASE_SUSPEND)); |
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321 ttw(str(TTrDrvErase, "es" NL)); |
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322 |
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323 // if erase has finished then all is ok |
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324 if (*dev.addr & 0x80) { |
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325 ffsdrv_amd_erase_end(); |
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326 tlw(led_off(LED_ERASE_SUSPEND)); |
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327 return; |
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328 } |
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329 |
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330 // NOTEME: As there is no way to be absolutely certain that erase |
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331 // doesn't finish between last poll and the following erase suspend |
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332 // command, we assume that the erase suspend is safe even though the |
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333 // erase IS actually already finished. |
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334 |
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335 cpsr = int_disable(); |
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336 dev.state = DEV_ERASE_SUSPEND; |
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337 *dev.addr = 0xB0; |
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338 |
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339 // Wait for erase suspend to finish |
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340 while ((*dev.addr & 0x80) == 0) |
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341 ; |
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342 |
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343 int_enable(cpsr); |
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344 } |
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345 |
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346 void ffsdrv_amd_erase_resume(void) |
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347 { |
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348 uint32 cpsr; |
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349 |
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350 ttw(str(TTrDrvErase, "er" NL)); |
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351 |
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352 // NOTEME: See note in erase_suspend()... We assume that the erase |
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353 // resume is safe even though the erase IS actually already finished. |
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354 cpsr = int_disable(); |
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355 dev.state = DEV_ERASE; |
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356 *dev.addr = 0x30; |
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357 int_enable(cpsr); |
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358 |
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359 tlw(led_off(LED_ERASE_SUSPEND)); |
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360 } |
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361 |
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362 const struct ffsdrv_s ffsdrv = { |
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363 ffsdrv_null_init, |
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364 ffsdrv_amd_erase, |
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365 ffsdrv_amd_write_halfword, |
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366 ffsdrv_generic_write, |
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367 ffsdrv_amd_write_end, |
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368 ffsdrv_amd_erase_suspend, |
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369 ffsdrv_amd_erase_resume |
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370 }; |
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371 |
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372 #else |
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373 |
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374 /* |
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375 * This part will get compiled if we have real FFS (FFS_IN_RAM=0), |
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376 * but not allowed to write to flash (CONFIG_FLASH_WRITE=0). |
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377 */ |
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378 |
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379 const struct ffsdrv_s ffsdrv = { |
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380 ffsdrv_null_init, |
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381 ffsdrv_null_erase, |
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382 ffsdrv_null_write_halfword, |
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383 ffsdrv_null_write, |
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384 ffsdrv_null_write_end, |
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385 ffsdrv_null_erase_suspend, |
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386 ffsdrv_null_erase_resume |
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387 }; |
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388 |
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389 #endif |
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390 |
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391 |
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392 /****************************************************************************** |
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393 * Initialization |
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394 * |
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395 * Significantly simplified in FreeCalypso. |
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396 * |
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397 ******************************************************************************/ |
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398 |
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399 effs_t ffsdrv_init(void) |
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400 { |
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401 int error; |
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402 |
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403 tw(tr(TR_BEGIN, TrDrvInit, "drv_init() {\n")); |
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404 ttw(str(TTrDrvOther, "ffsdrv_init() {" NL)); |
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405 |
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406 dev.state = DEV_READ; |
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407 dev.atomlog2 = FFS_ATOM_LOG2; |
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408 dev.atomsize = 1 << dev.atomlog2; |
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409 dev.atomnotmask = dev.atomsize - 1; |
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410 |
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411 error = ffsdrv.init(); |
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412 |
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413 tw(tr(TR_FUNC, TrDrvInit, "dev.binfo = 0x%x\n", (unsigned int) dev.binfo)); |
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414 tw(tr(TR_FUNC, TrDrvInit, "dev.base = 0x%x\n", (unsigned int) dev.base)); |
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415 tw(tr(TR_FUNC, TrDrvInit, "dev.numblocks = %d\n", dev.numblocks)); |
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416 tw(tr(TR_FUNC, TrDrvInit, "dev.blocksize = %d\n", dev.blocksize)); |
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417 tw(tr(TR_FUNC, TrDrvInit, "dev.atomlog2/atomsize/atomnotmask = %d/%d/%x\n", |
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418 dev.atomlog2, dev.atomsize, dev.atomnotmask)); |
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419 tw(tr(TR_END, TrDrvInit, "} %d\n", error)); |
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420 ttw(ttr(TTrDrvOther, "} %d" NL, error)); |
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421 |
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422 return error; |
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423 } |