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annotate gsm-fw/riviera/init/Makefile @ 416:c2e14cc15c23

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flash erase-program-boot: implemented CRC check before flashing
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Tue, 17 Jun 2014 07:33:25 +0000
parents afceeeb2cba1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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129
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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1 CC= arm-elf-gcc
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 CFLAGS= -Os -fno-builtin -mthumb-interwork -mthumb
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
4 OBJS= create_RVtasks.o
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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5
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
6 all: ${OBJS}
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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7
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
8 clean:
7d7950d7f924 Riviera should be ready for the first TI fw build attempt
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
9 rm -f *.[oa] *errs