FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/abb+spi/abb.c @ 255:c33fb341faeb
ffstools/tiffs-rd/README deleted, superceded by ffstools/README
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Mon, 03 Feb 2014 06:35:29 +0000 |
parents | 47754cdb6248 |
children | 99e44a92274c |
rev | line source |
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1 /**********************************************************************************/ |
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ |
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3 /* */ |
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */ |
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */ |
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6 /* product is protected under copyright law and trade secret law as an */ |
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ |
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8 /* rights reserved. */ |
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9 /* */ |
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10 /* */ |
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11 /* Filename : abb.c */ |
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12 /* */ |
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13 /* Description : Functions to drive the ABB device. */ |
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14 /* The Serial Port Interface is used to connect the TI */ |
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15 /* Analog BaseBand (ABB). */ |
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16 /* It is assumed that the ABB is connected as the SPI */ |
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17 /* device 0. */ |
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18 /* */ |
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19 /* Author : Pascal PUEL */ |
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20 /* */ |
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21 /* Version number : 1.3 */ |
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22 /* */ |
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23 /* Date and time : 08/22/03 */ |
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24 /* */ |
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25 /* Previous delta : Creation */ |
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26 /* */ |
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27 /**********************************************************************************/ |
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28 |
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29 #include "../../include/config.h" |
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30 #include "../../L1/include/l1_confg.h" |
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31 #include "../../L1/include/l1_macro.h" |
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32 |
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33 #include "abb.h" |
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34 #include "../clkm.h" // for wait_ARM_cycles function |
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35 #include "abb_inline.h" |
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36 #include "../ulpd.h" // for FRAME_STOP definition |
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37 |
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38 #include "../../include/sys_types.h" |
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39 #include "../../riviera/rv/general.h" |
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40 #include "../../nucleus/nucleus.h" // for NUCLEUS functions and types |
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41 #include "../../L1/include/l1_types.h" |
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42 |
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43 #if 0 // FreeCalypso |
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44 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function |
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45 #endif |
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46 |
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47 #if (VCXO_ALGO == 1) |
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48 #include "../../L1/include/l1_ctl.h" |
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49 #endif |
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50 |
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51 #if (RF_FAM == 35) |
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52 #include "../../L1/cust0/l1_rf35.h" |
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53 #endif |
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54 |
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55 #if (RF_FAM == 12) |
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56 #include "../../L1/tpudrv/tpudrv12.h" |
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57 #include "../../L1/cust0/l1_rf12.h" |
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58 #endif |
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59 |
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60 #if (RF_FAM == 10) |
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61 #include "../../L1/cust0/l1_rf10.h" |
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62 #endif |
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63 |
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64 #if (RF_FAM == 8) |
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65 #include "../../L1/cust0/l1_rf8.h" |
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66 #endif |
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67 |
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68 #if (RF_FAM == 2) |
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69 #include "../../L1/cust0/l1_rf2.h" |
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70 #endif |
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71 |
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72 #if (ABB_SEMAPHORE_PROTECTION) |
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73 |
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74 static NU_SEMAPHORE abb_sem; |
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75 |
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76 /*-----------------------------------------------------------------------*/ |
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77 /* ABB_Sem_Create() */ |
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78 /* */ |
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79 /* This function creates the Nucleus semaphore to protect ABB accesses */ |
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80 /* against preemption. */ |
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81 /* No check on the result. */ |
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82 /* */ |
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83 /*-----------------------------------------------------------------------*/ |
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84 void ABB_Sem_Create(void) |
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85 { |
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86 // create a semaphore with an initial count of 1 and with FIFO type suspension. |
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87 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); |
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88 } |
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89 |
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90 #endif // ABB_SEMAPHORE_PROTECTION |
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91 |
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92 /*-----------------------------------------------------------------------*/ |
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93 /* ABB_Wait_IBIC_Access() */ |
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94 /* */ |
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95 /* This function waits for the first IBIC access. */ |
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96 /* */ |
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97 /*-----------------------------------------------------------------------*/ |
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98 void ABB_Wait_IBIC_Access(void) |
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99 { |
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100 #if (ANALOG ==1) |
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101 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access |
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102 // (i.e wait 60us + 10% security marge = 66us) |
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103 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); |
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104 #elif ((ANALOG ==2) || (ANALOG == 3)) |
148
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105 // Wait 6 x 32 KHz clock cycles for first IBIC access |
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106 // (i.e wait 187us + 10% security marge = 210us) |
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107 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); |
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108 #endif |
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109 } |
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110 |
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111 |
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112 |
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113 /*-----------------------------------------------------------------------*/ |
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114 /* ABB_Write_Register_on_page() */ |
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115 /* */ |
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116 /* This function manages all the spi serial transfer to write to an */ |
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117 /* ABB register on a specified page. */ |
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118 /* */ |
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119 /*-----------------------------------------------------------------------*/ |
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120 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) |
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121 { |
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122 volatile SYS_UWORD16 status; |
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123 |
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124 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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125 SPI_Ready_for_WR |
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126 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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127 |
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128 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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129 |
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130 // check if the semaphore has been correctly created and try to obtain it. |
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131 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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132 // as soon as the semaphore is released. |
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133 if(&abb_sem != 0) |
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134 { |
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135 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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136 } |
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137 #endif // ABB_SEMAPHORE_PROTECTION |
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138 |
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139 // set the ABB page for register access |
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140 ABB_SetPage(page); |
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141 |
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142 // Write value in reg_id |
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143 ABB_WriteRegister(reg_id, value); |
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144 |
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145 // set the ABB page for register access at page 0 |
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146 ABB_SetPage(PAGE0); |
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147 |
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148 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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149 // release the semaphore only if it has correctly been created. |
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150 if(&abb_sem != 0) |
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151 { |
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152 NU_Release_Semaphore(&abb_sem); |
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153 } |
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154 #endif // ABB_SEMAPHORE_PROTECTION |
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155 |
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156 // Stop the SPI clock |
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157 #ifdef SPI_CLK_LOW_POWER |
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158 SPI_CLK_DISABLE |
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159 #endif |
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160 } |
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161 |
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162 |
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163 /*-----------------------------------------------------------------------*/ |
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164 /* ABB_Read_Register_on_page() */ |
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165 /* */ |
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166 /* This function manages all the spi serial transfer to read one */ |
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167 /* ABB register on a specified page. */ |
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168 /* */ |
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169 /* Returns the real data value of the register. */ |
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170 /* */ |
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171 /*-----------------------------------------------------------------------*/ |
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172 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) |
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173 { |
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174 volatile SYS_UWORD16 status; |
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175 SYS_UWORD16 reg_val; |
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176 |
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177 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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178 SPI_Ready_for_RDWR |
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179 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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180 |
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181 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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182 |
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183 // check if the semaphore has been correctly created and try to obtain it. |
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184 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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185 // as soon as the semaphore is released. |
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186 if(&abb_sem != 0) |
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187 { |
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188 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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189 } |
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190 #endif // ABB_SEMAPHORE_PROTECTION |
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191 |
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192 /* set the ABB page for register access */ |
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193 ABB_SetPage(page); |
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194 |
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195 /* Read selected ABB register */ |
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196 reg_val = ABB_ReadRegister(reg_id); |
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197 |
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198 /* set the ABB page for register access at page 0 */ |
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199 ABB_SetPage(PAGE0); |
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200 |
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201 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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202 // release the semaphore only if it has correctly been created. |
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203 if(&abb_sem != 0) |
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204 { |
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205 NU_Release_Semaphore(&abb_sem); |
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206 } |
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207 #endif // ABB_SEMAPHORE_PROTECTION |
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208 |
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209 // Stop the SPI clock |
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210 #ifdef SPI_CLK_LOW_POWER |
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211 SPI_CLK_DISABLE |
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212 #endif |
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213 |
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214 return (reg_val); // Return result |
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215 } |
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216 |
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217 /*------------------------------------------------------------------------*/ |
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218 /* ABB_free_13M() */ |
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219 /* */ |
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220 /* This function sets the 13M clock working in ABB. A wait loop */ |
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221 /* is required to allow first slow access to ABB clock register. */ |
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222 /* */ |
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223 /* WARNING !! : this function must not be protected by semaphore !! */ |
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224 /* */ |
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225 /*------------------------------------------------------------------------*/ |
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226 void ABB_free_13M(void) |
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227 { |
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228 volatile SYS_UWORD16 status; |
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229 |
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230 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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231 SPI_Ready_for_WR |
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232 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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233 |
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234 ABB_SetPage(PAGE0); |
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235 |
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236 // This transmission frees the CLK13 in ABB. |
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237 ABB_WriteRegister(TOGBR2, 0x08); |
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238 |
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239 // Wait for first IBIC access |
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240 ABB_Wait_IBIC_Access(); |
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241 |
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242 // SW Workaround : This transmission has to be done twice. |
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243 ABB_WriteRegister(TOGBR2, 0x08); |
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244 |
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245 // Wait for first IBIC access |
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246 ABB_Wait_IBIC_Access(); |
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247 |
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248 // Stop the SPI clock |
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249 #ifdef SPI_CLK_LOW_POWER |
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250 SPI_CLK_DISABLE |
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251 #endif |
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252 } |
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253 |
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254 |
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255 |
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256 /*------------------------------------------------------------------------*/ |
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257 /* ABB_stop_13M() */ |
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258 /* */ |
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259 /* This function stops the 13M clock in ABB. */ |
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260 /* */ |
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261 /*------------------------------------------------------------------------*/ |
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262 void ABB_stop_13M(void) |
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263 { |
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264 volatile SYS_UWORD16 status; |
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265 |
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266 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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267 SPI_Ready_for_WR |
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268 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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269 |
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270 ABB_SetPage(PAGE0); |
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271 |
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272 // Set ACTIVMCLK = 0. |
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273 ABB_WriteRegister(TOGBR2, 0x04); |
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274 |
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275 // Wait for first IBIC access |
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276 ABB_Wait_IBIC_Access(); |
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277 |
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278 // Stop the SPI clock |
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279 #ifdef SPI_CLK_LOW_POWER |
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280 SPI_CLK_DISABLE |
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281 #endif |
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282 } |
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283 |
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284 |
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285 |
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286 /*------------------------------------------------------------------------*/ |
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287 /* ABB_Read_Status() */ |
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288 /* */ |
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289 /* This function reads and returns the value of VRPCSTS ABB register. */ |
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290 /* */ |
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291 /*------------------------------------------------------------------------*/ |
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292 SYS_UWORD16 ABB_Read_Status(void) |
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293 { |
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294 volatile SYS_UWORD16 status; |
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295 SYS_UWORD16 reg_val; |
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296 |
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297 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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298 SPI_Ready_for_WR |
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299 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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300 |
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301 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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302 |
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303 // check if the semaphore has been correctly created and try to obtain it. |
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304 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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305 // as soon as the semaphore is released. |
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306 if(&abb_sem != 0) |
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307 { |
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308 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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309 } |
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310 #endif // ABB_SEMAPHORE_PROTECTION |
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311 |
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312 ABB_SetPage(PAGE0); |
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313 |
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314 #if (ANALOG == 1) || (ANALOG == 2) |
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315 ABB_SetPage(PAGE0); |
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316 reg_val = ABB_ReadRegister(VRPCSTS); |
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317 #elif (ANALOG == 3) |
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318 ABB_SetPage(PAGE1); |
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319 reg_val = ABB_ReadRegister(VRPCCFG); |
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320 #endif |
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321 |
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322 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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323 // release the semaphore only if it has correctly been created. |
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324 if(&abb_sem != 0) |
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325 { |
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326 NU_Release_Semaphore(&abb_sem); |
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327 } |
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328 #endif // ABB_SEMAPHORE_PROTECTION |
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329 |
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330 // Stop the SPI clock |
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331 #ifdef SPI_CLK_LOW_POWER |
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332 SPI_CLK_DISABLE |
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333 #endif |
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334 |
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335 return (reg_val); |
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336 } |
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337 |
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338 /*------------------------------------------------------------------------*/ |
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339 /* ABB_on() */ |
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340 /* */ |
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341 /* This function configures ABB registers to work in ON condition */ |
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342 /* */ |
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343 /*------------------------------------------------------------------------*/ |
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344 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) |
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345 { |
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346 volatile SYS_UWORD16 status; |
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347 #if ((ANALOG ==2) || (ANALOG == 3)) |
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348 SYS_UWORD32 reg; |
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349 #endif |
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350 |
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351 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 |
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352 if (bRecoveryFlag) |
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353 { |
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354 // RESTITUTE 13MHZ CLOCK TO ABB |
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355 //--------------------------------------------------- |
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356 ABB_free_13M(); |
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357 |
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358 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) |
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359 //--------------------------------------------------- |
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360 ABB_free_13M(); |
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361 } |
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362 |
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363 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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364 SPI_Ready_for_RDWR |
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365 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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366 |
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367 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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368 |
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369 // check if the semaphore has been correctly created and try to obtain it. |
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370 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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371 // as soon as the semaphore is released. |
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372 if(&abb_sem != 0) |
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373 { |
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374 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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375 } |
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376 #endif // ABB_SEMAPHORE_PROTECTION |
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377 |
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378 ABB_SetPage(PAGE0); |
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379 |
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380 // This transmission disables MADC,AFC,VDL,VUL modules. |
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381 ABB_WriteRegister(TOGBR1, 0x0155); |
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382 |
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383 #if (ANALOG == 1) |
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384 // This transmission disables Band gap fast mode Enable BB charge. |
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385 ABB_WriteRegister(VRPCCTL2, 0x1fc); |
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386 |
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387 /* *********** DC/DC enabling selection ************************************************************** */ |
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388 // This transmission changes the register page in OMEGA for usp to pg1. |
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389 ABB_SetPage(PAGE1); |
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390 |
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391 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */ |
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392 { |
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393 SYS_UWORD8 vrpcctrl3_data; |
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394 |
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395 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) |
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396 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035 |
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397 #else |
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398 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 |
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399 #endif |
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400 |
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401 if(modules & DCDC) // check if the DCDC is enabled |
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402 { |
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403 vrpcctrl3_data |= 0x0002; // set DCDCEN |
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404 } |
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405 |
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406 // This access disables the DCDC. |
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407 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); |
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408 } |
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409 |
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410 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ |
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411 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ |
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412 /* ***************************************************************************************************/ |
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413 #if (BOARD==6)&& (ANALOG==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) |
148
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414 // This transmission enables Omega test register. |
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415 ABB_WriteRegister(TAPCTRL, 0x01); |
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416 |
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417 // This transmission select Omega test instruction. |
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418 ABB_WriteRegister(TAPREG, TSPTEST1); |
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419 |
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420 // This transmission disables Omega test register. |
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421 ABB_WriteRegister(TAPCTRL, 0x00); |
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422 #endif |
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423 /* *************************************************************************************************** */ |
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424 |
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425 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue |
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426 { |
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427 // This transmission changes SIM power supply to 3 volts. |
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428 ABB_WriteRegister(VRPCCTRL1, 0x45); |
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429 } |
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430 |
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431 ABB_SetPage(PAGE0); |
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432 |
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433 // This transmission enables selected OMEGA modules. |
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434 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); |
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435 |
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436 if(modules & MADC) // check if the ADC is enabled |
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437 { |
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438 // This transmission connects the resistive divider to MB and BB. |
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439 ABB_WriteRegister(BCICTL1, 0x0005); |
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440 } |
154
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441 #elif ((ANALOG == 2) || (ANALOG == 3)) |
148
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442 // Restore the ABB checks and debouncing if start on TESTRESETZ |
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443 |
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444 // This transmission changes the register page in the ABB for usp to pg1. |
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445 ABB_SetPage(PAGE1); |
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446 |
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447 // This transmission sets the AFCCK to CKIN/2. |
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448 ABB_WriteRegister(AFCCTLADD, 0x01); |
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449 |
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450 // This transmission enables the tapreg. |
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451 ABB_WriteRegister(TAPCTRL, 0x01); |
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452 |
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453 // This transmission enables access to page 2. |
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454 ABB_WriteRegister(TAPREG, 0x01b); |
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455 |
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456 // This transmission changes the register page in the ABB for usp to pg2. |
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457 ABB_SetPage(PAGE2); |
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458 |
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459 #if (ANALOG == 2) |
148
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460 // Restore push button environment |
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461 ABB_WriteRegister(0x3C, 0x07); |
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462 |
154
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463 #elif (ANALOG == 3) |
148
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464 |
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465 // Restore push button environment |
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466 ABB_WriteRegister(0x3C, 0xBF); |
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467 |
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468 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ |
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469 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
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470 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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471 #endif |
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472 // This transmission enables access to page 0. |
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473 ABB_SetPage(PAGE0); |
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|
474 |
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475 // reset bit MSKINT1 , if set by TESTRESET |
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476 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; |
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|
477 |
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|
478 ABB_WriteRegister(VRPCSTS, reg); |
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|
479 |
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|
480 ABB_SetPage(PAGE2); |
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|
481 |
63750f70796d
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|
482 // Restore default for BG behavior in sleep mode |
63750f70796d
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parents:
diff
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|
483 ABB_WriteRegister(VRPCAUX, 0xBF); |
63750f70796d
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parents:
diff
changeset
|
484 |
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parents:
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|
485 // Restore default for deboucing length |
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|
486 ABB_WriteRegister(VRPCLDO, 0x00F); |
63750f70796d
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parents:
diff
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|
487 |
63750f70796d
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parents:
diff
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|
488 // Restore default for INT1 generation, wait time in switch on, checks in switch on |
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parents:
diff
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|
489 ABB_WriteRegister(VRPCABBTST, 0x0002); |
63750f70796d
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parents:
diff
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|
490 |
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491 #endif |
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|
492 |
63750f70796d
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parents:
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|
493 // This transmission changes the register page in the ABB for usp to pg1. |
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|
494 ABB_SetPage(PAGE1); |
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diff
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|
495 |
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|
496 // This transmission sets tapinst to id code. |
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parents:
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|
497 ABB_WriteRegister(TAPREG, 0x0001); |
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parents:
diff
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|
498 |
63750f70796d
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parents:
diff
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|
499 // This transmission disables TAPREG access. |
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parents:
diff
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|
500 ABB_WriteRegister(TAPCTRL, 0x00); |
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parents:
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|
501 |
63750f70796d
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|
502 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows |
63750f70796d
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parents:
diff
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|
503 // This transmission enables BB charge and BB bridge connection for BB measurements. |
63750f70796d
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parents:
diff
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|
504 ABB_WriteRegister(BCICONF, 0x060); |
63750f70796d
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parents:
diff
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|
505 |
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|
506 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ |
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507 #if (ANALOG == 3) |
148
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508 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO |
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509 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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510 #endif |
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511 #endif |
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|
512 |
63750f70796d
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parents:
diff
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|
513 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ |
63750f70796d
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parents:
diff
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|
514 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
63750f70796d
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parents:
diff
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|
515 /* ****************************************************************************************************/ |
63750f70796d
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diff
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|
516 |
63750f70796d
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diff
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|
517 // This transmission enables the tapreg. |
63750f70796d
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parents:
diff
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|
518 ABB_WriteRegister(TAPCTRL, 0x01); |
63750f70796d
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parents:
diff
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|
519 |
63750f70796d
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parents:
diff
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|
520 // This transmission select ABB test instruction. |
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521 ABB_WriteRegister(TAPREG, TSPEN); |
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522 |
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523 // This transmission changes the register page in ABB for usp to pg0. |
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524 ABB_SetPage(PAGE0); |
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525 |
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526 // This transmission enables selected ABB modules. |
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527 ABB_WriteRegister(TOGBR1, modules >> 6); |
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528 |
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529 // enable MB & BB resistive bridges for measurements |
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530 if(modules & MADC) // check if the ADC is enabled |
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531 { |
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532 // This transmission connects the resistive divider to MB and BB. |
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533 ABB_WriteRegister(BCICTL1, 0x0001); |
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534 } |
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535 |
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536 /********* Sleep definition part ******************/ |
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537 // This transmission changes the register page in the ABB for usp to pg1. |
154
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538 #if (ANALOG == 2) |
148
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539 ABB_SetPage(PAGE1); |
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540 |
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541 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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542 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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543 |
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544 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); |
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545 |
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546 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. |
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547 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; |
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548 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); |
154
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549 #elif (ANALOG == 3) |
148
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550 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); |
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551 #endif |
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552 // This transmission changes the register page in the ABB for usp to pg0. |
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553 ABB_SetPage(PAGE0); |
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554 #endif |
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555 |
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556 // SW workaround for initialization of the audio parts of the ABB to avoid white noise |
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557 // C.f. BUG1941 |
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558 // Set VDLR and VULR bits |
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559 // Write TOGBR1 register |
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560 // This transmission enables selected ABB modules. |
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561 ABB_WriteRegister(TOGBR1, 0x0A); |
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562 |
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563 // wait for 1 ms |
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564 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); |
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565 |
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566 // Reset VDLS and VULS bits |
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567 // Write TOGBR1 register |
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568 // This transmission enables selected ABB modules. |
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569 ABB_WriteRegister(TOGBR1, 0x05); |
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570 |
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571 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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572 // release the semaphore only if it has correctly been created. |
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573 if(&abb_sem != 0) |
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574 { |
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575 NU_Release_Semaphore(&abb_sem); |
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576 } |
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577 #endif // ABB_SEMAPHORE_PROTECTION |
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578 |
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|
579 // Stop the SPI clock |
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580 #ifdef SPI_CLK_LOW_POWER |
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581 SPI_CLK_DISABLE |
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582 #endif |
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583 } |
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|
584 |
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|
585 |
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|
586 |
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587 /*-----------------------------------------------------------------------*/ |
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588 /* ABB_Read_ADC() */ |
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589 /* */ |
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590 /* This function manages all the spi serial transfer to read all the */ |
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591 /* ABB ADC conversion channels. */ |
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592 /* Stores the result in Buff parameter. */ |
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593 /* */ |
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594 /*-----------------------------------------------------------------------*/ |
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595 void ABB_Read_ADC(SYS_UWORD16 *Buff) |
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|
596 { |
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597 volatile SYS_UWORD16 status; |
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|
598 |
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599 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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600 SPI_Ready_for_RDWR |
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601 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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|
602 |
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603 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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|
604 |
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|
605 // check if the semaphore has been correctly created and try to obtain it. |
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606 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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607 // as soon as the semaphore is released. |
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608 if(&abb_sem != 0) |
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|
609 { |
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610 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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611 } |
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|
612 #endif // ABB_SEMAPHORE_PROTECTION |
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|
613 |
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|
614 // This transmission changes the register page in the ABB for usp to pg0. |
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615 ABB_SetPage(PAGE0); |
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|
616 |
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|
617 /* Read all ABB ADC registers */ |
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618 *Buff++ = ABB_ReadRegister(VBATREG); |
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619 *Buff++ = ABB_ReadRegister(VCHGREG); |
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620 *Buff++ = ABB_ReadRegister(ICHGREG); |
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621 *Buff++ = ABB_ReadRegister(VBKPREG); |
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622 *Buff++ = ABB_ReadRegister(ADIN1REG); |
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|
623 *Buff++ = ABB_ReadRegister(ADIN2REG); |
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624 *Buff++ = ABB_ReadRegister(ADIN3REG); |
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625 |
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626 #if (ANALOG ==1) |
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627 *Buff++ = ABB_ReadRegister(ADIN4XREG); |
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628 *Buff++ = ABB_ReadRegister(ADIN5YREG); |
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629 #elif (ANALOG ==2) |
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630 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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631 #elif (ANALOG == 3) |
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632 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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633 *Buff++ = ABB_ReadRegister(ADIN5REG); |
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634 #endif // ANALOG |
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635 |
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636 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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637 // release the semaphore only if it has correctly been created. |
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638 if(&abb_sem != 0) |
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639 { |
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640 NU_Release_Semaphore(&abb_sem); |
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641 } |
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642 #endif // ABB_SEMAPHORE_PROTECTION |
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643 |
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644 // Stop the SPI clock |
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645 #ifdef SPI_CLK_LOW_POWER |
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646 SPI_CLK_DISABLE |
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647 #endif |
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648 } |
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649 |
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650 |
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651 |
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652 /*-----------------------------------------------------------------------*/ |
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653 /* ABB_Conf_ADC() */ |
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654 /* */ |
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655 /* This function manages all the spi serial transfer to: */ |
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656 /* - select the ABB ADC channels to be converted */ |
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657 /* - enable/disable EOC interrupt */ |
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658 /* */ |
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659 /*-----------------------------------------------------------------------*/ |
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660 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) |
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661 { |
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662 volatile SYS_UWORD16 status; |
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663 SYS_UWORD16 reg_val; |
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664 |
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665 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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666 SPI_Ready_for_RDWR |
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667 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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668 |
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669 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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670 |
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671 // check if the semaphore has been correctly created and try to obtain it. |
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672 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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673 // as soon as the semaphore is released. |
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674 if(&abb_sem != 0) |
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675 { |
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676 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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677 } |
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678 #endif // ABB_SEMAPHORE_PROTECTION |
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679 |
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680 // This transmission changes the register page in the ABB for usp to pg0. |
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681 ABB_SetPage(PAGE0); |
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682 |
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683 /* select ADC channels to be converted */ |
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684 #if (ANALOG == 1) |
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685 ABB_WriteRegister(MADCCTRL1, Channels); |
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686 #elif ((ANALOG == 2) || (ANALOG == 3)) |
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687 ABB_WriteRegister(MADCCTRL, Channels); |
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688 #endif |
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689 |
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690 reg_val = ABB_ReadRegister(ITMASK); |
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691 |
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692 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. |
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693 if(ItVal == EOC_INTENA) |
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694 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); |
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695 else if(ItVal == EOC_INTMASK) |
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696 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); |
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697 |
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698 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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699 // release the semaphore only if it has correctly been created. |
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700 if(&abb_sem != 0) |
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701 { |
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702 NU_Release_Semaphore(&abb_sem); |
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703 } |
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704 #endif // ABB_SEMAPHORE_PROTECTION |
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705 |
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706 // Stop the SPI clock |
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707 #ifdef SPI_CLK_LOW_POWER |
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708 SPI_CLK_DISABLE |
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709 #endif |
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710 } |
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711 |
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712 |
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713 |
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714 |
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715 /*------------------------------------------------------------------------*/ |
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716 /* ABB_sleep() */ |
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717 /* */ |
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718 /* This function disables the DCDC and returns to PAGE 0. It stops then */ |
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719 /* the 13MHz clock in ABB. A wait loop s required to allow */ |
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720 /* first slow access to ABB clock register. */ |
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721 /* */ |
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722 /* WARNING !! : this function must not be protected by semaphore !! */ |
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723 /* */ |
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724 /* Returns AFC value. */ |
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725 /* */ |
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726 /*------------------------------------------------------------------------*/ |
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727 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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728 { |
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729 volatile SYS_UWORD16 status; |
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730 SYS_UWORD32 afcout_index; |
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diff
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731 volatile SYS_UWORD16 nb_it; |
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732 SYS_UWORD16 reg_val; |
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733 |
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734 // table for AFC allowed values during Sleep mode. First 5th elements |
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735 // are related to positive AFC values, last 5th to negative ones. |
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736 static const SYS_UWORD32 Afcout_T[10] = |
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737 {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; |
148
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738 |
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739 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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740 SPI_Ready_for_RDWR |
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741 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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742 |
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743 // COMPUTATION AND PROGRAMMING OF AFC VALUE |
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744 //--------------------------------------------------- |
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745 if(afc & 0x1000) |
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746 afcout_index = ((afc + 512)>>10) + 1; |
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747 else |
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748 afcout_index = (afc + 512)>>10; |
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749 |
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750 if (sleep_performed == FRAME_STOP) // Big sleep |
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751 { |
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752 #if ((ANALOG == 2) || (ANALOG == 3)) |
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753 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// |
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754 #endif |
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755 |
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756 } |
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757 else // Deep sleep |
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758 { |
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759 #if(ANALOG == 1) |
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760 // SELECTION OF AFC TEST MODE FOR OMEGA |
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761 //--------------------------------------------------- |
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762 // This test configuration allows access on the AFCOUT register |
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763 ABB_SetPage(PAGE1); |
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764 |
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765 // This transmission enables OMEGA test register. |
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766 ABB_WriteRegister(TAPCTRL, 0x01); |
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767 |
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768 // This transmission selects OMEGA test instruction. |
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769 ABB_WriteRegister(TAPREG, AFCTEST); |
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770 |
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771 // Set AFCOUT to 0. |
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772 ABB_WriteRegister(AFCOUT, 0x00 >> 6); |
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773 |
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774 ABB_SetPage(PAGE0); |
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775 |
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776 #elif (ANALOG == 2) |
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777 // This configuration allows access on the AFCOUT register |
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778 ABB_SetPage(PAGE1); |
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779 |
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780 // Read AFCCTLADD value and enable USP access to AFCOUT register |
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781 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); |
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782 |
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783 ABB_WriteRegister(AFCCTLADD, reg_val); |
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784 |
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785 // Set AFCOUT to 0. |
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786 ABB_WriteRegister(AFCOUT, 0x00); |
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787 |
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788 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. |
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789 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; |
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790 |
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791 ABB_WriteRegister(BCICONF, reg_val); |
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792 |
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793 // Disable the ABB test mode |
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794 ABB_WriteRegister(TAPCTRL, 0x00); |
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795 |
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796 ABB_SetPage(PAGE0); |
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797 |
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798 // Read BCICTL1 value and cut the measurement bridge of MB. |
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799 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; |
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800 |
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801 ABB_WriteRegister(BCICTL1, reg_val); |
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802 #endif |
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803 |
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804 #if (ANALOG == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected |
148
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805 // in Syren during sleep mode. BB charge stays enabled |
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806 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission |
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807 // change the register page in IOTA for usp to pg1 |
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808 |
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809 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode |
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810 |
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811 ABB_SetPage(PAGE0); |
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812 #endif |
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813 |
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814 // switch off MADC, AFC, AUXDAC, VOICE. |
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815 ABB_WriteRegister(TOGBR1, 0x155); |
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|
816 |
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817 // Switch off Analog supply LDO |
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818 //----------------------------- |
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819 #if (ANALOG == 1) |
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820 ABB_SetPage(PAGE1); |
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821 |
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822 // Read VRPCCTL3 register value and switch off VR3. |
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823 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; |
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824 |
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825 ABB_WriteRegister(VRPCCTRL3, reg_val); |
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826 |
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827 #elif (ANALOG == 2) |
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828 // Read VRPCSTS register value and extract status of meaningfull inputs. |
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829 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; |
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830 |
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831 if (reg_val == 0x30) |
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832 { |
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833 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. |
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834 ABB_WriteRegister(VRPCDEV, 0x02); |
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835 } |
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836 |
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837 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". |
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838 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
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839 |
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840 #elif (ANALOG == 3) |
148
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841 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed |
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842 // start the SLPDLY counter in order to switch the ABB in sleep mode |
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843 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission |
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844 // set Syren sleep bit |
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845 /* |
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846 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". |
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847 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
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848 */ |
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849 #endif |
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850 |
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851 // Switch to low frequency clock |
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852 ABB_stop_13M(); |
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853 } |
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854 |
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855 // Stop the SPI clock |
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856 #ifdef SPI_CLK_LOW_POWER |
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857 SPI_CLK_DISABLE |
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858 #endif |
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859 |
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860 #if (OP_L1_STANDALONE == 1) |
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861 #if (CHIPSET == 12) |
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862 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull |
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863 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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864 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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865 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0 |
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866 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode |
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867 #endif |
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868 #endif |
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869 return(Afcout_T[afcout_index]); |
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870 } |
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871 |
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872 |
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873 /*------------------------------------------------------------------------*/ |
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874 /* ABB_wakeup() */ |
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875 /* */ |
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876 /* This function sets the 13MHz clock working in ABB. A wait loop */ |
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877 /* is required to allow first slow access to ABB clock register. */ |
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878 /* Then it re-enables DCDC and returns to PAGE 0. */ |
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879 /* */ |
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880 /* WARNING !! : this function must not be protected by semaphore !! */ |
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881 /* */ |
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882 /*------------------------------------------------------------------------*/ |
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883 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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884 { |
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885 volatile SYS_UWORD16 status; |
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886 SYS_UWORD16 reg_val; |
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887 |
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888 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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889 SPI_Ready_for_RDWR |
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890 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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891 |
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892 if (sleep_performed == FRAME_STOP) // Big sleep |
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893 { |
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894 #if ((ANALOG == 2) || (ANALOG == 3)) |
148
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895 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// |
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896 #endif |
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897 } |
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898 else // Deep sleep |
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899 { |
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900 #if (OP_L1_STANDALONE == 1) |
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901 #if (CHIPSET == 12) |
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902 // restore context from |
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903 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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904 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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905 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 |
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|
906 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode |
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907 #endif |
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908 #endif |
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909 |
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910 // Restitutes 13MHZ Clock to ABB |
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911 ABB_free_13M(); |
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912 |
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913 // Switch ON Analog supply LDO |
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914 #if (ANALOG == 1) |
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915 ABB_SetPage(PAGE1); |
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916 |
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917 // Read VRPCCTL3 register value and switch on VR3. |
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918 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; |
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919 |
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920 ABB_WriteRegister(VRPCCTRL3, reg_val); |
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921 ABB_SetPage(PAGE0); |
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922 #endif |
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923 |
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924 // This transmission switches on MADC, AFC. |
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925 ABB_WriteRegister(TOGBR1, 0x280); |
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|
926 |
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927 // This transmission sets the AUXAFC2. |
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928 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); |
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929 |
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930 // This transmission sets the AUXAFC1. |
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931 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); |
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932 |
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933 #if (ANALOG == 1) |
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934 // Remove AFC test mode |
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935 ABB_SetPage(PAGE1); |
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936 |
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937 // This transmission select Omega test instruction. |
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938 ABB_WriteRegister(TAPREG, TSPTEST1); |
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939 |
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940 // Disable test mode selection |
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941 // This transmission disables Omega test register. |
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942 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); |
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943 |
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944 ABB_SetPage(PAGE0); |
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945 |
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946 #elif (ANALOG == 2) |
148
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947 ABB_SetPage(PAGE1); |
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948 |
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949 // Read AFCCTLADD register value and disable USP access to AFCOUT register. |
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950 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; |
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951 |
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952 ABB_WriteRegister(AFCCTLADD, reg_val); |
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953 |
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954 // Read BCICONF register value and enable BB measurement bridge enable BB charge. |
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955 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; |
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956 |
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957 ABB_WriteRegister(BCICONF, reg_val); |
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958 |
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959 |
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960 /* *************************************************************************************************** */ |
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961 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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962 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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963 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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964 |
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965 // Enable the ABB test mode |
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966 ABB_WriteRegister(TAPCTRL, 0x01); |
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967 ABB_WriteRegister(TAPREG, TSPEN); |
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968 ABB_SetPage(PAGE0); |
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969 |
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970 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. |
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971 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; |
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972 |
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973 ABB_WriteRegister(BCICTL1, reg_val); |
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974 #endif |
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975 |
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976 #if (ANALOG == 3) |
148
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977 |
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978 ABB_SetPage(PAGE1); |
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979 |
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980 /* *************************************************************************************************** */ |
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981 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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982 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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983 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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984 |
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985 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ |
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986 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
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987 /* ****************************************************************************************************/ |
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988 |
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989 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register |
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990 // This transmission enables IOTA test register |
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991 |
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992 ABB_WriteRegister(TAPREG, TSPEN); |
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993 // This transmission select IOTA test instruction |
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994 // This transmission select IOTA test instruction |
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995 /**************************************************************************************************** */ |
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996 |
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997 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission |
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998 #endif |
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999 } |
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1000 |
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1001 // Stop the SPI clock |
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1002 #ifdef SPI_CLK_LOW_POWER |
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1003 SPI_CLK_DISABLE |
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1004 #endif |
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1005 } |
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1006 |
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1007 /*------------------------------------------------------------------------*/ |
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1008 /* ABB_wa_VRPC() */ |
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1009 /* */ |
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1010 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ |
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1011 /* according to the ABB used. */ |
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1012 /* */ |
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1013 /*------------------------------------------------------------------------*/ |
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1014 void ABB_wa_VRPC(SYS_UWORD16 value) |
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1015 { |
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1016 volatile SYS_UWORD16 status; |
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1017 |
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1018 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1019 SPI_Ready_for_WR |
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1020 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1021 |
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1022 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1023 |
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1024 // check if the semaphore has been correctly created and try to obtain it. |
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1025 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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1026 // as soon as the semaphore is released. |
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1027 if(&abb_sem != 0) |
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1028 { |
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1029 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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1030 } |
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1031 #endif // ABB_SEMAPHORE_PROTECTION |
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1032 |
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1033 ABB_SetPage(PAGE1); |
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1034 |
154
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1035 #if (ANALOG == 1) |
148
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1036 // This transmission initializes the VRPCCTL1 register. |
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1037 ABB_WriteRegister(VRPCCTRL1, value); |
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1038 |
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1039 #elif (ANALOG == 2) |
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1040 // This transmission initializes the VRPCSIM register. |
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1041 ABB_WriteRegister(VRPCSIM, value); |
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1042 |
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1043 #elif (ANALOG == 3) |
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1044 // This transmission initializes the VRPCSIMR register. |
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1045 ABB_WriteRegister(VRPCSIMR, value); |
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1046 |
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1047 #endif |
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1048 |
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1049 ABB_SetPage(PAGE0); |
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1050 |
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1051 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1052 // release the semaphore only if it has correctly been created. |
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1053 if(&abb_sem != 0) |
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1054 { |
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1055 NU_Release_Semaphore(&abb_sem); |
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1056 } |
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1057 #endif // ABB_SEMAPHORE_PROTECTION |
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1058 |
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1059 // Stop the SPI clock |
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1060 #ifdef SPI_CLK_LOW_POWER |
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1061 SPI_CLK_DISABLE |
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1062 #endif |
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1063 } |
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1064 |
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1065 |
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1066 /*-----------------------------------------------------------------------*/ |
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1067 /* ABB_Write_Uplink_Data() */ |
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1068 /* */ |
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1069 /* This function uses the SPI to write to ABB uplink buffer. */ |
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1070 /* */ |
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1071 /*-----------------------------------------------------------------------*/ |
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1072 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) |
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1073 { |
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1074 SYS_UWORD8 i; |
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1075 volatile SYS_UWORD16 status; |
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1076 |
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1077 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1078 SPI_Ready_for_WR |
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1079 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1080 |
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1081 // Select Page 0 for TOGBR2 |
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1082 ABB_SetPage(PAGE0); |
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1083 |
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1084 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 |
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1085 ABB_WriteRegister(TOGBR2, 0x10); |
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1086 |
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1087 // Clear, assuming that it works like IBUFPTR of Vega |
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1088 ABB_WriteRegister(TOGBR2, 0x0); |
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1089 |
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1090 // Write the ramp data |
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1091 for (i=0;i<16;i++) |
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1092 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); |
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1093 |
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1094 // Stop the SPI clock |
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1095 #ifdef SPI_CLK_LOW_POWER |
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1096 SPI_CLK_DISABLE |
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1097 #endif |
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1098 } |
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1099 |
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1100 //////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// |
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1101 |
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1102 #if (ANALOG == 3) |
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1103 |
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1104 // Syren Sleep configuration function -------------------------- |
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1105 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) |
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1106 { |
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1107 volatile SYS_UWORD16 status,sl_ldo_stat; |
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1108 |
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1109 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission |
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1110 // change the register page in ABB for usp to pg1 |
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1111 |
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1112 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value |
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1113 |
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1114 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); |
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1115 |
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1116 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration |
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1117 |
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1118 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission |
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1119 // change the register page in ABB for usp to pg0 |
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1120 } |
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1121 #endif |
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1122 |
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1123 |
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1124 #if (OP_L1_STANDALONE == 0) |
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1125 /*-----------------------------------------------------------------------*/ |
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1126 /* ABB_Power_Off() */ |
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1127 /* */ |
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1128 /* This function uses the SPI to switch off the ABB. */ |
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1129 /* */ |
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1130 /*-----------------------------------------------------------------------*/ |
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1131 void ABB_Power_Off(void) |
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1132 { |
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1133 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). |
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1134 NU_Sleep (30); |
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1135 |
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1136 // Wait also until <ON/OFF> key is released. |
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1137 // This is needed to avoid, if the power key is pressed for a long time, to switch |
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1138 // ON-switch OFF the mobile, until the power key is released. |
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1139 #if((ANALOG == 1) || (ANALOG == 2)) |
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1140 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { |
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1141 #elif(ANALOG == 3) |
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1142 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { |
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1143 #endif |
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1144 |
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1145 NU_Sleep (1); } |
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1146 |
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1147 #if 0 // FreeCalypso |
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1148 BZ_KeyBeep_OFF(); |
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1149 #endif |
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1150 |
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1151 #if(ANALOG == 1) |
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1152 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); |
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1153 #elif((ANALOG == 2) || (ANALOG == 3)) |
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1154 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); |
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1155 #endif |
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1156 } |
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1157 #endif |