FreeCalypso > hg > freecalypso-sw

annotate rvinterf/include/etm.h @ 344:c51d6b3748c3

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
OSL: os_SuspendTask() done
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 03 May 2014 19:20:05 +0000
parents c146f38d2b5f
children 42719fa3e6af
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
181
6800c2cc8c51 gsm-fw/riviera/rvm/rvm_use_id_list.h: tab fix
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 /*
6800c2cc8c51 gsm-fw/riviera/rvm/rvm_use_id_list.h: tab fix
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 * This header file contains various definitions for talking to ETM.
6800c2cc8c51 gsm-fw/riviera/rvm/rvm_use_id_list.h: tab fix
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 */
6800c2cc8c51 gsm-fw/riviera/rvm/rvm_use_id_list.h: tab fix
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
4
182
13a0348ffce4 rvinterf/etm: checkpointing not-yet-compilable code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 181
diff changeset
5 #define ETM_USE_ID 0x001E0004
188
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
6
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
7 /* ETM Module IDs */
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
8 enum {
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
9 ETM_TM3 = 0x00, // Use of old TM3 protocol
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
10 ETM_CORE = 0x01,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
11 ETM_TMT = 0x02, // Pseudo module
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
12 ETM_SH = 0x03, // Pseudo module
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
13 ETM_TM3_MISC = 0x04, // Pseudo module - Target side
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
14 ETM_RF = 0x05,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
15 ETM_IMEI = 0x06,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
16 ETM_FFS2 = 0x07,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
17 ETM_AUDIO = 0x08,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
18 ETM_TPU = 0x09, // Not official part ETM
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
19 ETM_PWR = 0x0A,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
20 ETM_BT = 0x0B,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
21 ETM_L23 = 0x0C,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
22 ETM_RESERVED10 = 0x0D,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
23 ETM_RESERVED11 = 0x0E,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
24 ETM_RESERVED12 = 0x0F,
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
25
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
26 ETM_CUST = 0xC0, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
27 ETM_CUST1 = 0xC1, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
28 ETM_CUST2 = 0xC2, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
29 ETM_CUST3 = 0xC3, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
30 ETM_CUST4 = 0xC4, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
31 ETM_CUST5 = 0xC5, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
32 ETM_CUST6 = 0xC6, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
33 ETM_CUST7 = 0xC7, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
34 ETM_CUST8 = 0xC8, // Customize id
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
35
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
36 ETM_TEST = 0xAA, // used for test of dll's
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
37 ETM_TASK = 0xEE, // ETM TASK in Target
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
38
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
39 ETM_FFS1 = 0x70
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
40 };
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
41
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
42 /* ETM_CORE opcodes */
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
43 #define TMCORE_OPC_MEM 0x61
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
44 #define TMCORE_OPC_ECHO 0x62
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
45 #define TMCORE_OPC_RESET 0x63
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
46 #define TMCORE_OPC_DEBUG 0x64
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
47 #define TMCORE_OPC_VERSION 0x65
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
48 #define TMCORE_OPC_CODEC_RD 0x66
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
49 #define TMCORE_OPC_CODEC_WR 0x67
9f4f331ac24d fc-tmsh: implemented handling of ETM_CORE responses
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 182
diff changeset
50 #define TMCORE_OPC_DIEID 0x68