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annotate loadtools/scripts/pirelli.init @ 73:c54c6ad1c66f

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pirexplore: added rtccomp command to read RTC compensation registers
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 26 Jul 2013 21:12:03 +0000
parents 9a77b3395747
children 5b53cad88637
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fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 # This phone has 3 memory chip selects:
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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2 #
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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3 # nCS0: flash chip select 1
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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4 # nCS1: RAM chip select
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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5 # nCS3: flash chip select 2
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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6 #
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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7 # All 3 chip select lines go to the same physical IC, a RAM/flash MCP.
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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8 # We set WS=4 for all 3 here, copying what OsmocomBB does. The access
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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9 # time listed in the datasheet is 70 ns for both RAM and flash, and per
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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10 # my math setting WS=3 *might* work, but it could be marginal, so let's
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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11 # play it safe for now.
fa3e9a5665bd loadtool hw configuration files created for the Pirelli
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9a77b3395747 Pirelli ADD22 configuration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 18
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9a77b3395747 Pirelli ADD22 configuration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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17 # We also need to switch the CS4/ADD22 pin from its default function
9a77b3395747 Pirelli ADD22 configuration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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18 # of CS4 to the needed ADD22.
9a77b3395747 Pirelli ADD22 configuration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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9a77b3395747 Pirelli ADD22 configuration
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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