FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/nucleus/sd_defs.h @ 1004:c83d3346d4b9
gsm-fw band-aid for voice calls: pcmdata.c: advertise support for FR codec only
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Sat, 19 Mar 2016 07:01:54 +0000 |
parents | afceeeb2cba1 |
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rev | line source |
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1 /************************************************************************* |
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2 * |
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3 * Copyright Mentor Graphics Corporation 2002 |
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4 * All Rights Reserved. |
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5 * |
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6 * THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS |
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7 * THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS |
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8 * SUBJECT TO LICENSE TERMS. |
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9 * |
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10 *************************************************************************/ |
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11 |
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12 /************************************************************************* |
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13 * |
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14 * FILE NAME VERSION |
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15 * |
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16 * sd_defs.h Nucleus PLUS\ARM925\Code Composer 1.14.1 |
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17 * |
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18 * COMPONENT |
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19 * |
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20 * SD - Serial Driver |
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21 * |
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22 * DESCRIPTION |
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23 * |
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24 * This file contains constant definitions and function macros |
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25 * for the Serial Driver module. |
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26 * |
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27 * DATA STRUCTURES |
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28 * |
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29 * SD_PORT : Structure to keep all needed info. about a port. |
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30 * |
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31 * DEPENDENCIES |
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32 * |
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33 * none |
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34 * |
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35 * |
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36 *************************************************************************/ |
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37 #ifndef SD_DEFS_H |
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38 #define SD_DEFS_H |
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39 |
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40 /**************** User configurable section *************************/ |
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41 |
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42 /* |
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43 * The OMAP1510 version of this code found in XVilka's original |
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44 * code drop supported two UARTs numbered 1 and 2. |
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45 * In this proof-of-concept Calypso version this numbering |
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46 * has been retained, even though all other Calypso software |
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47 * I know of uses 0 and 1. |
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48 * The FreeNucleus UART numbers have been mapped as follows: |
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49 * 1 = MODEM, 2 = IrDA |
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50 */ |
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51 |
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52 /* The base addresses for the seperate UART registers. */ |
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53 #define SD_UART_MODEM_BASE 0xFFFF5800 |
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54 #define SD_UART_IRDA_BASE 0xFFFF5000 |
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55 |
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56 /* Macros for specifying which UART to use. */ |
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57 #define SD_UART1 1 |
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58 #define SD_UART2 2 |
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59 |
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60 #define SD_UART_MODEM 1 |
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61 #define SD_UART_IRDA 2 |
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62 |
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63 #define SD_MAX_UARTS 2 |
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64 |
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65 /* These use specific type names, putting the register name |
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66 in the macro, because these macros are used by port specific |
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67 sections of code and will most likely have different names |
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68 on other UARTS. */ |
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69 /*************************************/ |
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70 /* Receive Holding Register - RHR (R)*/ |
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71 /*************************************/ |
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72 #define RHR_OFFSET 0x00 |
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73 |
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74 /**************************************/ |
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75 /* Transmit Holding Register - THR (W)*/ |
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76 /**************************************/ |
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77 #define THR_OFFSET 0x00 |
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78 |
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79 /****************************************/ |
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80 /* Interrupt Enable Register - IER (R/W)*/ |
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81 /****************************************/ |
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82 #define IER_OFFSET 0x01 |
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83 #define IER_RX_HOLDING_REG 0x01 /* bit 0 - Recieve Holding Register Interrupt |
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84 - Enabled When Set */ |
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85 #define IER_TX_HOLDING_REG 0x02 /* bit 1 - Transmit Holding Register Interrupt |
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86 - Enabled When Set */ |
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87 #define IER_RX_LINE_STATUS 0x04 /* bit 2 - recieve Line Status Interrupt |
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88 - Enabled When Set */ |
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89 #define IER_MODEM_STATUS 0x08 /* bit 3 - Modem Status Interrupt |
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90 - Enabled When Set */ |
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91 |
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92 |
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93 /************************************/ |
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94 /* FIFO Control Register - FCR (W) */ |
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95 /************************************/ |
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96 #define FCR_OFFSET 0x02 |
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97 #define FCR_FIFO_ENABLED 0x01 /* bit 0 - Enabled When Set */ |
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98 #define FCR_RCVR_TRIG_LEVEL 0x00 /* bit 6:bit 7 - 8 Bytes Trigger Level */ |
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99 #define FCR_FIFO_RESET 0x06 /* bit 1-2 - TX/RX FIFO Reset When Set */ |
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100 |
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101 /************************************************/ |
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102 /* Interrupt Identification Register - IIR (IIR)*/ |
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103 /************************************************/ |
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104 #define IIR_OFFSET 0x02 |
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105 #define IIR_TYPE_MASK 0x0000003E /* bit 5:bit 1 */ |
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106 #define IIR_PENDING 0x00000001 /* ISR pending bit - 0=pending, 1=not pending */ |
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107 #define IIR_RX_TIMEOUT 0x0000000C /* 1 1 0 - RX time out Priority 2 */ |
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108 #define IIR_RX_RDY 0x00000004 /* 0 1 0 - Received Data Ready Priority 2 */ |
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109 #define IIR_TX_RDY 0x00000002 /* 0 0 1 - Transmitter Holding Reg Empty Priority 3 */ |
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110 #define IIR_RX_LINE_STAT 0x00000006 /* 0 1 1 - Receive Line Status Priority 1 */ |
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111 |
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112 /**************************************/ |
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113 /* Latch Control Register - LCR (R/W)*/ |
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114 /**************************************/ |
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115 #define LCR_OFFSET 0x03 |
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116 #define LCR_5_BIT_WORD 0x00 /* 0 0 - 5 Bit Word */ |
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117 #define LCR_6_BIT_WORD 0x01 /* 0 1 - 6 Bit Word */ |
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118 #define LCR_7_BIT_WORD 0x02 /* 1 0 - 7 Bit Word */ |
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119 #define LCR_8_BIT_WORD 0x03 /* 1 1 - 8 Bit Word */ |
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120 |
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121 #define LCR_STOP_BIT_1 0x00 /* 1 stop bit */ |
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122 #define LCR_STOP_BIT_2 0x04 /* 2 stop bit */ |
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123 |
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124 #define LCR_PARITY_ENABLE 0x08 /* bit 3 - Enable Parity Bit Generation and Check |
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125 - Enabled When Set */ |
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126 #define LCR_PARITY_DISABLE 0x00 /* bit 3 - Enable Parity Bit Generation and Check |
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127 - Enabled When Set */ |
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128 #define LCR_PARITY_EVEN 0x10 /* bit 4 - Odd/Even Parity Generation and Check |
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129 - Even When Set */ |
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130 #define LCR_PARITY_ODD 0x00 /* bit 4 - Odd/Even Parity Generation and Check |
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131 - Odd When Set */ |
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132 #define LCR_BREAK_SET 0x40 /* bit 6 - Force Break Control ( Tx o/p low) |
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133 - Forced When Set */ |
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134 #define LCR_NO_BREAK 0x00 /* bit 6 - Normal operating conditions */ |
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135 #define LCR_DIV_EN 0x80 /* Enable access to DLL and DLH */ |
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136 |
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137 /*************************************/ |
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138 /* Modem Control Register - MCR (R/W)*/ |
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139 /*************************************/ |
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140 #define MCR_OFFSET 0x04 |
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141 |
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142 #define MCR_DTR_LOW 0x01 /* bit 0 - Set DCD Signal Low/High - DCD Low when Set */ |
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143 #define MCR_RTS_LOW 0x02 /* bit 1 - Set RTS Signal Low/High - RTS Low when Set */ |
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144 #define MCR_NORMAL_MODE 0x00 /* bit 4 - normal operating mode */ |
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145 #define MCR_LOOP_BACK 0x10 /* bit 4 - enable loopback mode */ |
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146 #define MCR_TCR_TLR 0x40 /* bit 6 - enable access to TCR and TLR */ |
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147 #define MCR_CLKSEL 0x80 /* bit 7 - enable clk/4 */ |
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148 #define MCR_Not_Used 0x0C /* bit 2,bit 3 - not used */ |
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149 |
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150 |
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151 /* The Following Registers are Status Registers which Report conditions within the */ |
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152 /* UART/PPP during operation. The defined values are masks to ensure that the register*/ |
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153 /* flags are correctly accessed */ |
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154 |
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155 /*********************************/ |
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156 /* Line Status Register - LSR (R)*/ |
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157 /*********************************/ |
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158 #define LSR_OFFSET 0x05 |
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159 #define LSR_RX_DATA_READY 0x01 /* bit 0 - Data Received and Saved in Holding Reg |
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160 - Set when Valid */ |
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161 #define LSR_OVERRUN_ERROR 0x02 /* bit 1 - Overrun Error Occured |
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162 - Set When Valid */ |
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163 #define LSR_PARITY_ERROR 0x04 /* bit 2 - Parity Error Occured |
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164 - Set When Valid */ |
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165 #define LSR_FRAMING_ERROR 0x08 /* bit 3 - Framing Error Occured |
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166 - Set When Valid */ |
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167 #define LSR_BREAK_ERROR 0x10 /* bit 4 - Break Error Occured |
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168 - Set When Valid */ |
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169 #define LSR_TX_HOLD_EMPTY 0x20 /* bit 5 - Tx Holding Register is empty and ready |
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170 - Set When Valid */ |
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171 #define LSR_TX_HOLD_FULL 0x00 /* bit 5 - Tx Holding Register is Full */ |
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172 |
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173 #define LSR_TX_EMPTY 0x40 /* bit 6 - 1= Tx Holding and shift registers are empty */ |
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174 #define LSR_TX_FULL 0x00 /* bit 6 - 0= Tx Holding and shift registers are full */ |
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175 |
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176 #define LSR_FIFO_ERROR 0x80 /* bit 7 - At Least one of b4 - b2 has occurred |
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177 - Set When Valid */ |
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178 |
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179 /**********************************/ |
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180 /* Modem Status Register - MSR (R)*/ |
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181 /**********************************/ |
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182 #define MSR_OFFSET 0x06 |
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183 |
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184 /******************************************/ |
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185 /* Supplementary Status Register - SSR (R)*/ |
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186 /******************************************/ |
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187 #define SSR_OFFSET 0x11 /* Supplementary Status Reg Offset */ |
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188 #define SSR_TX_FIFO_FULL 0x01 /* bit 0 - Tx FIFO full - Set when full */ |
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189 |
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190 /***************************************/ |
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191 /* Mode Definition Register - MDR (R/W)*/ |
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192 /***************************************/ |
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193 #define MDR_OFFSET 0x08 |
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194 #define MDR_UART_MODE 0x00 /* bit 2:bit 0 - 0 0 0 - Uart Mode */ |
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195 #define MDR_AUTO_MODE 0x02 /* bit 2:bit 0 - 0 1 0 - AutoBaud Mode */ |
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196 #define MDR_RESET_MODE 0x07 /* bit 2:bit 0 - 1 1 1 - Reset Mode */ |
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197 |
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198 /***********************************************/ |
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199 /* Divisor for baud-rate generation - DLH (R/W)*/ |
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200 /***********************************************/ |
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201 #define DLH_OFFSET 0x01 |
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202 |
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203 /***********************************************/ |
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204 /* Divisor for baud-rate generation - DLL (R/W)*/ |
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205 /***********************************************/ |
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206 #define DLL_OFFSET 0x00 |
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207 |
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208 |
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209 /* These use generic type names, leaving off the register name |
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210 in the macro, because they are used by generic sections of |
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211 code which will not require changes for other UARTS. Only the |
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212 bits these correspond to should change. */ |
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213 |
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214 /* UART Line Control Register Bits */ |
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215 #define SD_PARITY_NONE LCR_PARITY_DISABLE |
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216 #define SD_PARITY_EVEN LCR_PARITY_EVEN |
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217 #define SD_PARITY_ODD LCR_PARITY_ODD |
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218 |
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219 #define SD_DATA_BITS_5 LCR_5_BIT_WORD |
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220 #define SD_DATA_BITS_6 LCR_6_BIT_WORD |
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221 #define SD_DATA_BITS_7 LCR_7_BIT_WORD |
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222 #define SD_DATA_BITS_8 LCR_8_BIT_WORD |
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223 |
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224 #define SD_STOP_BITS_1 LCR_STOP_BIT_1 |
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225 #define SD_STOP_BITS_2 LCR_STOP_BIT_2 |
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226 |
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227 #define SD_MODE_NORMAL MCR_NORMAL_MODE |
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228 #define SD_MODE_AUTO_ECHO MCR_NOT_USED |
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229 #define SD_MODE_LOCAL_LOOP MCR_LOOP_BACK |
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230 #define SD_MODE_REMOTE_LOOP MCR_NOT_USED |
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231 |
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232 /* Define default Serial Driver settings for this board */ |
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233 #define DEFAULT_UART_PORT SD_UART_IRDA |
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234 #define DEFAULT_PPP_BAUD 57600 |
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235 #define DEFAULT_UART_BAUD 115200 |
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236 #define DEFAULT_UART_DATA DATA_BITS_8 |
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237 #define DEFAULT_UART_STOP STOP_BITS_1 |
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238 #define DEFAULT_UART_PARITY PARITY_NONE |
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239 #define DEFAULT_UART_MODE MODE_NORMAL |
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240 #define DEFAULT_UART_BUFFER 100 |
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241 |
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242 /* Define data structures for management of a serial port. */ |
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243 |
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244 typedef struct SD_INIT_STRUCT |
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245 { |
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246 UINT32 data_mode; |
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247 UINT32 base_address; |
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248 |
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249 /* The following elements should generic accross other |
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250 platforms. */ |
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251 NU_SEMAPHORE *sd_semaphore; |
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252 UINT32 com_port; |
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253 UINT32 data_bits; |
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254 UINT32 stop_bits; |
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255 UINT32 parity; |
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256 UINT32 baud_rate; |
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257 UINT32 vector; |
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258 UINT32 driver_options; |
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259 UINT32 sd_buffer_size; |
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260 |
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261 UINT32 parity_errors; |
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262 UINT32 frame_errors; |
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263 UINT32 overrun_errors; |
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264 UINT32 busy_errors; |
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265 UINT32 general_errors; |
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266 |
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267 CHAR *rx_buffer; |
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268 INT rx_buffer_read; |
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269 INT rx_buffer_write; |
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270 volatile INT rx_buffer_status; |
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271 |
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272 /* All of the following elements are required by PPP, do not modify. */ |
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273 UINT32 communication_mode; |
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274 CHAR *tx_buffer; |
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275 INT tx_buffer_read; |
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276 INT tx_buffer_write; |
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277 volatile INT tx_buffer_status; |
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278 |
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279 } SD_PORT; |
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280 |
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281 /* Defines to be used by application */ |
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282 #define MODE_NORMAL SD_MODE_NORMAL |
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283 #define MODE_AUTO_ECHO SD_MODE_AUTO_ECHO |
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284 #define MODE_LOCAL_LOOP SD_MODE_LOCAL_LOOP |
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285 #define MODE_REMOTE_LOOP SD_MODE_REMOTE_LOOP |
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286 |
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287 #define STOP_BITS_1 SD_STOP_BITS_1 |
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288 #define STOP_BITS_2 SD_STOP_BITS_2 |
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289 |
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290 #define UART1 SD_UART1 |
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291 #define UART2 SD_UART2 |
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292 |
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293 /* Defines to determine communication mode */ |
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294 #define SERIAL_MODE 0 |
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295 #define SERIAL_MOUSE 3 |
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296 /* MDM_NETWORK and MDM_TERMINAL do not need to be defined here |
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297 since they are defined in PPP. */ |
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298 |
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299 /*********************************************************************** |
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300 Note: everything below should be genric. |
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301 */ |
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302 |
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303 #define NU_SERIAL_PORT SD_PORT |
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304 #define PARITY_NONE SD_PARITY_NONE |
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305 #define PARITY_EVEN SD_PARITY_EVEN |
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306 #define PARITY_ODD SD_PARITY_ODD |
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307 |
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308 #define DATA_BITS_6 SD_DATA_BITS_6 |
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309 #define DATA_BITS_7 SD_DATA_BITS_7 |
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310 #define DATA_BITS_8 SD_DATA_BITS_8 |
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311 |
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312 #define NU_SD_Put_Char SDC_Put_Char |
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313 #define NU_SD_Get_Char SDC_Get_Char |
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314 #define NU_SD_Put_String SDC_Put_String |
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315 #define NU_SD_Init_Port SDC_Init_Port |
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316 #define NU_SD_Data_Ready SDC_Data_Ready |
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317 |
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318 #define NU_UART_SUCCESS 0 |
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319 #define NU_INVALID_PARITY -1 |
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320 #define NU_INVALID_DATA_BITS -2 |
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321 #define NU_INVALID_STOP_BITS -3 |
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322 #define NU_INVALID_BAUD -4 |
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323 #define NU_INVALID_COM_PORT -5 |
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324 #define NU_INVALID_DATA_MODE -6 |
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325 #define NU_UART_LIST_FULL -7 |
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326 #define NU_INVALID_MOUSE_MODE -8 |
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327 |
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328 #define NU_BUFFER_FULL 1 |
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329 #define NU_BUFFER_DATA 2 |
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330 #define NU_BUFFER_EMPTY 3 |
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331 |
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332 /* Deifine IO macros. */ |
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333 |
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334 /* 8 bit access */ |
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335 #define SD_OUTBYTE(reg, data) ( (*( (volatile UINT8 *) (reg) ) ) = (UINT8) (data) ) |
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336 |
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337 #define SD_INBYTE(reg) ( *( (volatile UINT8 *) (reg) ) ) |
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338 |
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339 /* 16 bit access */ |
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340 #define SD_OUTWORD(reg, data) ( (*( (volatile UINT16 *) (reg) ) ) = (data) ) |
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341 |
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342 #define SD_INWORD(reg) ( *( (volatile UINT16 *) (reg) ) ) |
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343 |
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344 /* 32 bit access */ |
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345 #define SD_OUTDWORD(reg, data) ( (*( (volatile UINT32 *) (reg) ) ) = (data) ) |
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346 |
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347 #define SD_INDWORD(reg) ( *( (volatile UINT32 *) (reg) ) ) |
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348 |
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349 /*Macro used for converting URT to SD_PORT. This is for PPP serial driver |
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350 backwards compatability. */ |
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351 #define URT_LAYER SD_PORT |
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352 |
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353 #define URT_TX_BUFFER_SIZE uart->sd_buffer_size |
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354 #define URT_Get_Char SDC_Get_Char |
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355 #define URT_Put_Char SDC_Put_Char |
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356 #define URT_Reset SDC_Reset |
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357 #define URT_Change_Communication_Mode SDC_Change_Communication_Mode |
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358 #define URT_Carrier SDC_Carrier |
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359 |
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360 |
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361 #endif /* ifndef SD_DEFS_H */ |