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annotate gsm-fw/sysglue/flashboot.S @ 876:c9f353b5d70c

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rvinterf/asyncshell/rxctl.c: buglet in the implementation of dis/enable commands
author Space Falcon <falcon@ivan.Harhan.ORG>
date Sat, 30 May 2015 07:50:05 +0000
parents 06ecb305f650
children a8fc7526935e
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
631
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 /*
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2 * This assembly module contains those bits which are specific to flashable
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3 * image builds only. It puts bits of code into several different sections.
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4 */
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5
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6 #include "../include/config.h"
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7
636
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8 #if FLASH_BOOT_VIA_BOOTROM
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9 /*
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10 * Put something sensible in the boot ROM overlay area, just for the
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11 * heck of it, or for extra robustness.
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12 */
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13 .section bootrom.overlay,"ax",%progbits
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14 .code 32
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15 .org 0
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16 b BootROM_disabled_entry
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17 #include "vectors.S"
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18 BootROM_disabled_entry:
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19 /* copy the boot ROM switch code to IRAM and jump to it */
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20 ldr r4, =__romswitch_flash_addr
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21 ldr r5, =__romswitch_ram_addr
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22 ldr r2, =__romswitch_size
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23 1: ldr r0, [r4], #4
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24 str r0, [r5], #4
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25 subs r2, r2, #4
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26 bhi 1b
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27 ldr pc, =__romswitch_ram_addr
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28
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29 .section bootrom.switch,"ax",%progbits
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30 .code 32
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31 .org 0
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32 @ enable the Calypso boot ROM
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33 ldr r1, =0xFFFFFB10
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34 mov r2, #0x0100
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35 strh r2, [r1]
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36 @ jump to it!
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37 mov pc, #0
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38 #endif
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39
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40 .section flashboot.text,"ax",%progbits
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41 .code 32
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42 .org 0
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43 #if FLASH_BOOT_VIA_BOOTROM
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44 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
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45 /* provide the necessary magic words for the boot ROM */
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46 .word 0
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47 .word _Flash_boot_entry
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48 #elif CONFIG_TARGET_C139
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49 /*
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50 * On this target we are going to put a special flash boot stage at 0x2000,
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51 * and then the actual gsm-fw image at the flash erase block boundary
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52 * at 0x10000. The following bits will be read by our intermediate
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53 * flash boot stage.
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54 */
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55 .asciz "FreeCalypso"
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56 .word _Flash_boot_entry
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57 #elif CONFIG_TARGET_C155
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58 /*
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59 * On this target the hand-off point between the bootloader and the main
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60 * fw image coincides with a flash erase block boundary, thus no need
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61 * for an intermediate flash boot stage. The following bits will appear
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62 * at 0x20000.
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63 */
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64 .asciz "FreeCalypso firmware for C155/156 target"
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65 .org 0xE0
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66 /* C155/156 bootloader jumps here */
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67 b _Flash_boot_entry
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68 #include "vectors.S"
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69 #else
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70 #error "Unsupported flash boot configuration"
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71 #endif
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72
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73 .globl _Flash_boot_entry
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74 _Flash_boot_entry:
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75 /* first order of business: configure flash and XRAM access */
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76 ldr r2, =0xFFFFFB00
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77 #if CONFIG_TARGET_PIRELLI
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78 mov r0, #0x00A4
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79 strh r0, [r2, #0]
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80 strh r0, [r2, #2]
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81 strh r0, [r2, #6]
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82 #else
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83 mov r0, #0x00A3
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84 strh r0, [r2, #0]
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85 strh r0, [r2, #2]
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86 #endif
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87 /*
634
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88 * On targets with 8 MiB flash (or XRAM) banks we need to switch the
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89 * CS4/ADD22 pin to the ADD22 function. We could do it for all targets
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90 * (not aware of any that need the pin to be CS4), but we strongly
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91 * prefer to have a consistent execution environment between flashImage
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92 * and ramImage, so let's only do this setting on those targets
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93 * on which we do it in ../../loadtools/scripts/*.init (for fc-xram).
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94 */
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95 #if CONFIG_TARGET_PIRELLI || CONFIG_TARGET_C155
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96 ldr r1, =0xFFFEF006
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97 mov r2, #0x0008
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98 strh r2, [r1]
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99 #endif
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100 /* we now have full access to all flash and RAM on the device */
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101 /* copy iram.text to where it's supposed to be */
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102 ldr r8, =__iramtext_flash_addr
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103 ldr r9, =__iramtext_ram_addr
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104 ldr r10, =__iramtext_size
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105 1: ldmia r8!, {r0-r7}
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106 stmia r9!, {r0-r7}
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107 subs r10, r10, #0x20
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108 bhi 1b
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109 /* likewise copy .data from flash to XRAM */
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110 ldr r8, =__initdata_flash_addr
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111 ldr r9, =__initdata_ram_addr
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112 ldr r10, =__initdata_size
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113 1: ldmia r8!, {r0-r7}
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114 stmia r9!, {r0-r7}
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115 subs r10, r10, #0x20
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116 bhi 1b
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117 /* boot path joins with fc-xram loadable builds */
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118 b _FlashorXram_entry