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annotate gsm-fw/bsp/dma.h @ 977:ce0ded19a769

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rvinterf: first attempt at TM3 memory read: omemdump command in fc-fsio
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Thu, 10 Dec 2015 04:00:08 +0000
parents afceeeb2cba1
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : dma.h
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12
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13 Description : DMA
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14
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15 Project : drivers
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16
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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18
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19 Version number : 1.6
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20
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21 Date and time : 01/30/01 10:22:23
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22
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23 Previous delta : 12/08/00 11:22:15
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24
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.dma.h
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26
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27 Sccs Id (SID) : '@(#) dma.h 1.6 01/30/01 10:22:23 '
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28
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29
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30 *****************************************************************************/
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31
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32 #include "../include/config.h"
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33
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34 /**** DMA configuration register ****/
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35
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36 #if (CHIPSET == 12)
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37
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38 #define DMA_GCR (MEM_DMA_ADDR + 0x0400)
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39 #define DMA_CAR (MEM_DMA_ADDR + 0x0404)
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40 #define DMA_SCR (MEM_DMA_ADDR + 0x0406)
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41 #define DMA_AR (MEM_DMA_ADDR + 0x040A)
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42
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43 #define DMA_CONFIG { \
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44 * (volatile unsigned short *) DMA_GCR = 0x0000; /* Force Autogating off */ \
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45 * (volatile unsigned short *) DMA_CAR |= 0x0001; /* Channel 0 allocated to DSP */ \
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46 * (volatile unsigned short *) DMA_SCR &= ~0x0001; /* Channel 0 is not secure */ \
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47 * (volatile unsigned short *) DMA_AR = 0x001C; /* Reset value */ \
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48 }
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49
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50 #else
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51
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52 // CONTROLLER_CONFIG register
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53 //---------------------------
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54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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55 #define DMA_CONFIG_ADDR MEM_DMA_ADDR
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56 #else
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57 #define DMA_CONFIG_ADDR (MEM_DMA_ADDR + 0x20)
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58 #endif
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59 #define DMA_CONFIG_BURST 0x1c /* length of burst */
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60
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61 // ALLOC_CONFIG register
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62 //---------------------------
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63 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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64 #define DMA_ALLOC_CONFIG_ADDR (MEM_DMA_ADDR + 0x02)
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65 #endif
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66 #define DMA_CONFIG_ALLOC1 0x01 /* allocation for channel 1 */
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67 #define DMA_CONFIG_ALLOC2 0x02 /* allocation for channel 2 */
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68
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69 // DMA Channel 1 configuration
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70 //---------------------------
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71
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72 // DMA1_RAD register
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73 //---------------------------
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74 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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75 #define DMA1_RAD_ADDR (MEM_DMA_ADDR + 0x10)
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76 #else
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77 #define DMA1_RAD_ADDR MEM_DMA_ADDR
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78 #endif
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79 #define DMA_RHEA_ADDR 0x07ff /* rhea start address */
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80 #define DMA_RHEA_CS 0xf800 /* rhea chip select */
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81
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82 // DMA1_RDPTH register
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83 //---------------------------
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84 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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85 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
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86 #else
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87 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x02)
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88 #endif
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89 #define DMA_RHEA_LENGTH 0x07ff /* rhea buffer length */
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90
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91 // DMA1_AAD register
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92 //---------------------------
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93 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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94 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x14)
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95 #else
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96 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x04)
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97 #endif
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98 #define DMA_API_ADDR 0x0fff /* API start address */
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99
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100 // DMA1_ALGTH register
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101 //---------------------------
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102 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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103 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
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104 #else
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105 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x06)
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106 #endif
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107 #define DMA_API_LENGTH 0x0fff /* API page length */
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108
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109 // DMA1_CTRL register
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110 //---------------------------
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111 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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112 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
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113 #else
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114 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x08)
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115 #endif
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116 #define DMA_CTRL_ENABLE 0x0001 /* DMA enable */
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117 #define DMA_CTRL_IDLE 0x0002 /* idle */
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118 #define DMA_CTRL_ONE_SHOT 0x0004
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119 #define DMA_CTRL_FIFO_MODE 0x0008
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120 #define DMA_CTRL_CUR_PAGE 0x0010 /* current page # */
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121 #define DMA_CTRL_MAS 0x0020
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122 #define DMA_CTRL_START 0x0040 /* DMA start */
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123 #define DMA_CTRL_IRQ_MODE 0x0080
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124 #define DMA_CTRL_IRQ_STATE 0x0100
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125 #define DMA_CTRL_RHEA_ABORT 0x0200
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126 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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127 #define DMA_CTRL_PRIORITY 0x1800 /* Number of additional reading on the bus */
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128 #endif
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129
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130 // DMA1_CUR_OFFSET_API register
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131 //---------------------------
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132 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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133 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
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134 #else
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135 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x0A)
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136 #endif
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137
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138
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139 // DMA Channel 2 configuration
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140 //---------------------------
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141
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142 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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143 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x20)
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144 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x22)
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145 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x24)
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146 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x26)
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147 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x28)
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148 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x2A)
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149 #else
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150 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x10)
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151 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
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152 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x14)
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153 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
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154 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
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155 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
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156 #endif
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157
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158 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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159 // DMA Channel 3 configuration
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160 //---------------------------
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161
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162 #define DMA3_RAD_ADDR (MEM_DMA_ADDR + 0x30)
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163 #define DMA3_RDPTH_ADDR (MEM_DMA_ADDR + 0x32)
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164 #define DMA3_AAD_ADDR (MEM_DMA_ADDR + 0x34)
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165 #define DMA3_ALGTH_ADDR (MEM_DMA_ADDR + 0x36)
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166 #define DMA3_CTRL_ADDR (MEM_DMA_ADDR + 0x38)
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167 #define DMA3_OFFSET_ADDR (MEM_DMA_ADDR + 0x3A)
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168
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169 // DMA Channel 4 configuration
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170 //---------------------------
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171
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172 #define DMA4_RAD_ADDR (MEM_DMA_ADDR + 0x40)
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173 #define DMA4_RDPTH_ADDR (MEM_DMA_ADDR + 0x42)
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174 #define DMA4_AAD_ADDR (MEM_DMA_ADDR + 0x44)
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175 #define DMA4_ALGTH_ADDR (MEM_DMA_ADDR + 0x46)
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176 #define DMA4_CTRL_ADDR (MEM_DMA_ADDR + 0x48)
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177 #define DMA4_OFFSET_ADDR (MEM_DMA_ADDR + 0x4A)
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178 #endif
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179
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180 /*---------------------------------------------------------------/
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181 /* DMA_ALLOCDMA() */
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182 /*--------------------------------------------------------------*/
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183 /* Parameters : none */
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184 /* Return : none */
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185 /* Functionality : alloc DMA channel */
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186 /*--------------------------------------------------------------*/
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187
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188 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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189 // WARNING :
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190 // Only the first two channels can be configured and the last two channels are forced to be controlled by the ARM
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191 #define DMA_ALLOCDMA(channel0, channel1, dma_burst,priority) { \
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192 * (volatile unsigned short *) DMA_CONFIG_ADDR = (dma_burst << 2) | (priority << 5); \
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193 * (volatile unsigned short *) DMA_ALLOC_CONFIG_ADDR = channel0 | (channel1 << 1) | 0x000C; \
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194 }
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195 #else
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196 #define DMA_ALLOCDMA(channel0, channel1,dma_burst,priority) (* (volatile unsigned short *) DMA_CONFIG_ADDR = channel0 | channel1 << 1 | dma_burst << 2 | priority << 5)
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197 #endif
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198
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199 #endif /* CHIPSET != 12 */
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200