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annotate gsm-fw/bsp/niq.c @ 977:ce0ded19a769

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rvinterf: first attempt at TM3 memory read: omemdump command in fc-fsio
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Thu, 10 Dec 2015 04:00:08 +0000
parents afceeeb2cba1
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : niq.c
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12
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13 Description : Nucleus IQ initializations
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14
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15 Project : Drivers
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16
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17 Author : proussel@ti.com Patrick Roussel.
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18
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19 Version number : 1.8
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20
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21 Date and time : 01/30/01 10:22:21
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22
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23 Previous delta : 12/19/00 14:22:24
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24
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.niq.c
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26
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27 Sccs Id (SID) : '@(#) niq.c 1.8 01/30/01 10:22:21 '
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28 *******************************************************************************/
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29
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30
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31 #include "../include/config.h"
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32 #include "../include/sys_types.h"
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33
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34 #include "mem.h"
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35 #include "rhea_arm.h"
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36 #include "inth.h"
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37 #include "iq.h"
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38
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39 extern SYS_FUNC irqHandlers[IQ_NUM_INT];
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40
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41 /*--------------------------------------------------------------*/
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42 /* IQ_Prty[IQ_NUM_INT] */
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43 /*--------------------------------------------------------------*/
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44 /* Parameters : none */
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45 /* Return : none */
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46 /* Functionality : IRQ priorities 0xFF means interrupt is masked*/
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47 /*--------------------------------------------------------------*/
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48
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49 #if (CHIPSET == 4)
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50 unsigned char IQ_Prty[IQ_NUM_INT] =
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51 {
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52 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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53 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02,
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54
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55 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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56 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03,
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57
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58 // AIRQ16 AIRQ17 AIRQ18 AIRQ19
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59 0x07, 0xFF, 0x02, 0x03
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60
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61 };
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62 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
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63 unsigned char IQ_Prty[IQ_NUM_INT] =
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64 {
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65 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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66 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02,
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67
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68 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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69 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03,
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70
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71 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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72 0x07, 0xFF, 0x02, 0x03, 0x0F, 0xFF, 0xFF, 0xFF,
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73
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74 // AIRQ24
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75 0xFF
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76
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77 };
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78 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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79 unsigned char IQ_Prty[IQ_NUM_INT] =
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80 {
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81 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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82 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02,
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83
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84 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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85 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03,
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86
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87 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20
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88 0x07, 0xFF, 0x02, 0x03, 0xFF
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89
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90 };
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91 #elif (CHIPSET == 12)
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92 unsigned char IQ_Prty[IQ_NUM_INT] =
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93 {
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94 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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95 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02,
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96
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97 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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98 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03,
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99
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100 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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101 0x07, 0xFF, 0x02, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,
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102
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103 // AIRQ24 AIRQ25 AIRQ26 AIRQ27 AIRQ28 AIRQ29 AIRQ30 AIRQ31
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104 0xFF, 0xFF, 0xFF, 0xFF, 0x02, 0xFF, 0xFF, 0xFF
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105
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106 };
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107 #else
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108 unsigned char IQ_Prty[IQ_NUM_INT] =
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109 {
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110 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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111 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02,
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112
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113 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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114 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03
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115
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116 };
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117 #endif
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118
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119 /*--------------------------------------------------------------*/
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120 /* IQ_LEVEL[IQ_NUM_INT] */
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121 /*--------------------------------------------------------------*/
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122 /* Parameters : none */
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123 /* Return : none */
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124 /* Functionality : IRQ sensitivity */
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125 /* 0: falling edge 1: low level (default) */
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126 /*--------------------------------------------------------------*/
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127
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128 #if (CHIPSET == 4)
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129 unsigned char IQ_LEVEL[IQ_NUM_INT] =
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130 {
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131 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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132 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
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133
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134 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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135 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01,
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diff changeset
136
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137 // AIRQ16 AIRQ17 AIRQ18 AIRQ19
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138 0x01, 0x01, 0x00, 0x00
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diff changeset
139
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140 };
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141 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
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142 unsigned char IQ_LEVEL[IQ_NUM_INT] =
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143 {
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diff changeset
144 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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145 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
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diff changeset
146
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147 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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148 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01,
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149
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150 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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diff changeset
151 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
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152
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153 // AIRQ24
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154 0x00
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155
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156 };
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157 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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158 unsigned char IQ_LEVEL[IQ_NUM_INT] =
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159 {
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diff changeset
160 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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161 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
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diff changeset
162
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diff changeset
163 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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diff changeset
164 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01,
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diff changeset
165
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166 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20
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167 0x01, 0x01, 0x00, 0x00, 0x00
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diff changeset
168
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169 };
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170 #elif (CHIPSET == 12)
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diff changeset
171 unsigned char IQ_LEVEL[IQ_NUM_INT] =
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172 {
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173 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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174 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
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diff changeset
175
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176 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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diff changeset
177 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01,
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diff changeset
178
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179 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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diff changeset
180 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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diff changeset
181
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182 // AIRQ24 AIRQ25 AIRQ26 AIRQ27 AIRQ28 AIRQ29 AIRQ30 AIRQ31
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183 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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184
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185 };
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186 #else
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187 unsigned char IQ_LEVEL[IQ_NUM_INT] =
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188 {
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189 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
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diff changeset
191
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192 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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193 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01
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diff changeset
194
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195 };
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196 #endif
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197
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198
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199 /*--------------------------------------------------------------*/
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200 /* IQ_FIQ_nIRQ[IQ_NUM_INT] */
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diff changeset
201 /*--------------------------------------------------------------*/
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diff changeset
202 /* Parameters : none */
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diff changeset
203 /* Return : none */
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parents:
diff changeset
204 /* Functionality : IRQ sensitivity */
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parents:
diff changeset
205 /* 0: falling edge 1: low level (default) */
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206 /*--------------------------------------------------------------*/
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parents:
diff changeset
207
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208 #if (CHIPSET == 4)
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diff changeset
209 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] =
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210 {
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parents:
diff changeset
211 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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diff changeset
212 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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parents:
diff changeset
213
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diff changeset
214 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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parents:
diff changeset
215 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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parents:
diff changeset
216
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parents:
diff changeset
217 // AIRQ16 AIRQ17 AIRQ18 AIRQ19
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parents:
diff changeset
218 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ
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parents:
diff changeset
219
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parents:
diff changeset
220 };
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diff changeset
221 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
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parents:
diff changeset
222 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] =
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diff changeset
223 {
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parents:
diff changeset
224 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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diff changeset
225 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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parents:
diff changeset
226
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parents:
diff changeset
227 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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parents:
diff changeset
228 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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diff changeset
229
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parents:
diff changeset
230 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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parents:
diff changeset
231 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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parents:
diff changeset
232
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
233 // AIRQ24
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
234 INTH_IRQ
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parents:
diff changeset
235
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parents:
diff changeset
236 };
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parents:
diff changeset
237 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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diff changeset
238 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] =
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parents:
diff changeset
239 {
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parents:
diff changeset
240 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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parents:
diff changeset
241 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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parents:
diff changeset
242
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
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parents:
diff changeset
243 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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diff changeset
244 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
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parents:
diff changeset
245
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
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parents:
diff changeset
246 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20
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parents:
diff changeset
247 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ
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parents:
diff changeset
248
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
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parents:
diff changeset
249 };
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parents:
diff changeset
250 #elif (CHIPSET == 12)
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parents:
diff changeset
251 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] =
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diff changeset
252 {
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parents:
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253 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7
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254 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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255
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256 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD
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diff changeset
257 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
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258
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259 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
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260 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ,
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261
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262 // AIRQ24 AIRQ25 AIRQ26 AIRQ27 AIRQ28 AIRQ29 AIRQ30 AIRQ31
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parents:
diff changeset
263 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ
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264
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265 };
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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266 #endif
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267
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268 /*--------------------------------------------------------------*/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
269 /* IQ_GetBuild */
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parents:
diff changeset
270 /*--------------------------------------------------------------*/
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parents:
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271 /* Parameters : none */
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parents:
diff changeset
272 /* Return : Return library build number */
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parents:
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273 /* Functionality : */
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parents:
diff changeset
274 /*--------------------------------------------------------------*/
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275
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parents:
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276 unsigned IQ_GetBuild(void)
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parents:
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277 {
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parents:
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278 return(IQ_BUILD);
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
279 }
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280
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parents:
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281
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parents:
diff changeset
282 /*--------------------------------------------------------------*/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
283 /* IQ_SetupInterrupts */
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
284 /*--------------------------------------------------------------*/
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parents:
diff changeset
285 /* Parameters : none */
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parents:
diff changeset
286 /* Return : none */
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parents:
diff changeset
287 /* Functionality : Set IRQ interrupt levels and unmask */
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parents:
diff changeset
288 /*--------------------------------------------------------------*/
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parents:
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289
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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290 void IQ_SetupInterrupts(void)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
291 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
292 int i;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
293 char prty;
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parents:
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294
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295 /* Setup all interrupts to IRQ with different levels */
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parents:
diff changeset
296 for (i=INTH_TIMER;i<=IQ_NUM_INT;i++ )
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parents:
diff changeset
297 {
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parents:
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298 prty = IQ_Prty[i];
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parents:
diff changeset
299 if (prty != 0xFF)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
300 {
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parents:
diff changeset
301 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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parents:
diff changeset
302 INTH_InitLevel(i, IQ_FIQ_nIRQ[i], prty, IQ_LEVEL[i]);
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parents:
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303 #else
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
304 INTH_InitLevel(i, INTH_IRQ, prty, IQ_LEVEL[i]);
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
305 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
306 }
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
307 INTH_DISABLEONEIT(i);
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
308 }
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
309 }
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parents:
diff changeset
310
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parents:
diff changeset
311 /*--------------------------------------------------------------*/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
312 /* IQ_InitWaitState */
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parents:
diff changeset
313 /*--------------------------------------------------------------*/
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
314 /* Parameters :rom, ram, spy, lcd, jtag */
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parents:
diff changeset
315 /* Return : none */
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
316 /* Functionality : Init wait states */
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parents:
diff changeset
317 /*--------------------------------------------------------------*/
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parents:
diff changeset
318
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parents:
diff changeset
319 void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
320 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
321 volatile char ws;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
322
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parents:
diff changeset
323 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS0;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
324 ws &= ~WS_MASK;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
325 ws |= rom;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
326 * (volatile SYS_UWORD16 *) MEM_REG_nCS0 = ws;
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parents:
diff changeset
327
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parents:
diff changeset
328 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS1;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
329 ws &= ~WS_MASK;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
330 ws |= ram;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
331 * (volatile SYS_UWORD16 *) MEM_REG_nCS1 = ws;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
332
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
333 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS2;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
334 ws &= ~WS_MASK;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
335 ws |= spy;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
336 * (volatile SYS_UWORD16 *) MEM_REG_nCS2 = ws;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
337
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
338 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS4;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
339 ws &= ~WS_MASK;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
340 ws |= lcd;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
341 * (volatile SYS_UWORD16 *) MEM_REG_nCS4 = ws;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
342
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
343 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11))
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
344 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS5;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
345 ws &= ~WS_MASK;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
346 ws |= jtag;
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
347 * (volatile SYS_UWORD16 *) MEM_REG_nCS5 = ws;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
348 #endif
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
349
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
350 }
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
351
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
352 void IQ_Unmask(unsigned irqNum)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
353 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
354 INTH_ENABLEONEIT(irqNum);
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
355 }
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
356
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
357 void IQ_Mask(unsigned irqNum)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
358 {
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
359 INTH_DISABLEONEIT(irqNum);
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
360 }
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
361
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
362 void IQ_MaskAll(void)
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
363 {
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
364 INTH_DISABLEALLIT;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
365 }
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
366
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
367
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
368 /*
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
369 * IQ_GetJtagId
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
370 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
371 * JTAG part identifier
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
372 */
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
373 SYS_UWORD16 IQ_GetJtagId(void)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
374 {
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
375 unsigned short v;
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
376
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
377 v = *( (volatile unsigned short *) (MEM_JTAGID_PART));
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
378 return(v);
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
379 }
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
380
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
381
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
382
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
383 /*
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
384 * IQ_GetDeviceVersion
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
385 *
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
386 * Read from CLKM module
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
387 */
45911ad957fd nuc-fw: beginning to integrate TI's BSP code
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
388 SYS_UWORD16 IQ_GetDeviceVersion(void)
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389 {
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390 SYS_UWORD16 v;
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391
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392 v = *( (volatile SYS_WORD16 *) (MEM_JTAGID_VER));
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393 return(v);
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394 }
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395
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396
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397 //// !!!! TO BE REMOVED IN NEXT CONDAT RELEASE >2.55
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398 /*
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399 * IQ_GetDeviceVersion
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400 *
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401 * Read from CLKM module
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402 */
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403 SYS_UWORD16 IQ_GetPoleStarVersion(void)
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404 {
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405 SYS_UWORD16 v;
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406
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407 v = *( (volatile SYS_UWORD16 *) (MEM_JTAGID_VER));
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408 return(v);
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409 }
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410
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411
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412
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413 /*
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414 * IQ_RamBasedLead
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415 *
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416 * Returns TRUE if the LEAD has RAM and needs to be downloaded
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417 *
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418 */
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419
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420 SYS_BOOL IQ_RamBasedLead(void)
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421 {
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422 unsigned short id;
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423
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424 id = IQ_GetJtagId();
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425
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426 #if (CHIPSET != 7)
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427 return ((id == SATURN || id == HERCRAM || id == 0xB2AC) ? 1 : 0);
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428 #else
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429 // Calypso G2 rev. A and Samson share the same JTAG ID
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430 return (0);
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431 #endif
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432 }
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433
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434 /*
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435 * IQ_Power
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436 *
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437 * Switch-on or off the board
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438 *
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439 * Parameters : BOOL power : 1 to power-on (maintain power)
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440 * 0 to power-off
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441 *
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442 * See A-Sample board specification
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443 */
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444 void IQ_Power(SYS_UWORD8 power)
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445 {
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446 // This is only implemented for the A-Sample
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447 }
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448
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449 /*
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450 * IQ_GetRevision
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451 *
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452 * Silicon revision - Read from JTAG version code
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453 */
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454 SYS_UWORD16 IQ_GetRevision(void)
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455 {
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456 unsigned short v;
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457
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458 v = *( (volatile unsigned short *) (MEM_JTAGID_VER));
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459 return(v);
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460 }
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461
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462 #if (TI_PROFILER == 1)
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463
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464 /*
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465 * IQ_InitLevel
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466 *
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467 * Parameters : interrupt, FIQ_nIRQ, priority, edge
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468 * Return : none
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469 * Functionality : initialize Interrupt Level Registers
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470 */
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471
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472 void IQ_InitLevel ( SYS_UWORD16 inputInt,
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473 SYS_UWORD16 FIQ_nIRQ,
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474 SYS_UWORD16 priority,
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475 SYS_UWORD16 edge )
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476 {
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477 volatile SYS_UWORD16 *inthLevelReg = (SYS_UWORD16 *) INTH_EXT_REG;
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478
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479 inthLevelReg = inthLevelReg + inputInt;
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480
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481 *inthLevelReg = (FIQ_nIRQ | (priority << 6) | (edge << 1));
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482 }
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483
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484 #endif