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annotate gsm-fw/L1/tpudrv/tpudrv.h @ 577:d70ebaea3003

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L1: tpudrv.c compiles
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 11 Aug 2014 06:32:10 +0000
parents 3a0ce0ea4035
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename tpudrv.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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9 /*
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10 * Device addresses - GCS000
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11 */
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12 // GSM 1.5 : TPU / TSP addresses
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13 //-------------------------------------
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15 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
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16 #define TPU_ADDR 0xFFFE0000L //omaps00090550 // Hercule / Ulysse / Samson
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17
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18 #define TPU_RAM (TPU_ADDR + 0x1400)
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19
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20 #define TPU_REG (TPU_ADDR + 0x1000)
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21 #define TSP_REG (TPU_ADDR + 0x0800)
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22 #define TPU_TIM (TPU_ADDR + 0x2000)
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24 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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25 #define TPU_ADDR 0xFFFF0000L // Strobe 1 address //omaps00090550
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26
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27 #define TPU_RAM 0xFFFF9000L // TPU RAM //omaps00090550
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29 #define TPU_REG (TPU_ADDR + 0x1000) // TPU register
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30 #define TSP_REG 0xFFFE0800L // TSP register //omaps00090550
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31 #define TPU_TIM 0xFFFE2000L // ULPD register //omaps00090550
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33 #elif (CHIPSET == 15)
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34 #define TPU_ADDR 0xFFFFF000L // Strobe 1 address //omaps00090550
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36 #define TPU_RAM 0xFFFF9000L // TPU RAM //omaps00090550
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38 #define TPU_REG (TPU_ADDR) // TPU register
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40 // TSP should be removed for Locosto. Leaving it as such as the TPU drivers are not yet ported.
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41 #define TSP_REG 0xFFFE0800L // TSP register //omaps00090550
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42 #define TPU_TIM 0xFFFE2000L // ULPD register //omaps00090550
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43
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44 #endif
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47 /*
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48 * Macros for defining TPU instructions
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49 */
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50 #define TPU_SLEEP 0
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51 #define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr))
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52 #define TPU_AT(time) (0x2000 | (((time + 5000) % 5000)))
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53 #define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo
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54 #define TPU_SYNC(time) (0x6000 | (time))
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55 #define TPU_WAIT(time) (0xA000 | (time))
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56 #define TPU_OFFSET(time) (0x4000 | (time))
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57 #define MOD5000(a) (((a) + 5000) % 5000)
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60 /*
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61 * TSP registers - defined in GCS004 - Time Serial Port
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62 */
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63 /*
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64 * in TPU address space
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65 */
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66 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
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67 // added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
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68 //-----------------------------------------------------
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69 #define TSP_CTRL1 0x00
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70 #define TSP_CTRL2 0x01
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71 #define TSP_TX_REG_1 0x04
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72 #define TSP_TX_REG_2 0x03
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73 #define TSP_TX_REG_3 0x02
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74 #define TSP_TX_REG_4 0x05
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75 #define TSP_ACT 0x06
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76 #define TSP_ACTX 0x07
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77 #define TSP_GAUGING_EN 0x11
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78 #define TSP_SPI_SET1 0x09
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79 #define TSP_SPI_SET2 0x0A
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80 #define TSP_SPI_SET3 0x0B
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81 #define TPU_IT_DSP_PG 0x10
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82 #define TSP_GAUGING_EN 0x11
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83
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84 /*
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85 * in ARM address space - defined in HYP004
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86 */
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87 #define TSP_RX_LSB (TSP_REG + 0x00)
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88 #define TSP_RX_MSB (TSP_REG + 0x02)
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89 #define TSP_TX_LSB (TSP_REG + 0x0c)
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90 #define TSP_TX_MSB (TSP_REG + 0x0a)
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91
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92 /*
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93 * TSP registers bit definitions
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94 */
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95 #define TC1_DEVICE0 0x00
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96 #define TC1_DEVICE1 0x20
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97 #define TC1_DEVICE2 0x40
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98 #define TC1_DEVICE3 0x60
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99 #define TC1_DEVICE4 0x80
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100 #define TC2_RD 0x01
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101 #define TC2_WR 0x02
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102 #define TC2_EDGE_TRIG 0x40
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103 #define TC2_RISING 0x80
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104 #define TSP_CLK_RISE 0x01
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105 #define TSP_ENA_POS 0x02
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106 #define TSP_ENA_EDGE 0x04
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107 #define GAUGING_START 0x01
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108 #define GAUGING_STOP 0x00
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109 #define TSP_ENA_POS_MSB 0x20
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110
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113 /*
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114 * TPU registers - defined in HYP002
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115 */
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116 // GSM 1.5 : TPU reg are 16-bit access
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117 //---------------------------------------
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118 #define TPU_CTRL (TPU_REG + 0x00)
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119 #define TPU_INT_CTRL (TPU_REG + 0x02)
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120 #define TPU_INT_STAT (TPU_REG + 0x04)
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121 #define TPU_OFFSET_REG (TPU_REG + 0x0C)
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122 #define TPU_SYNCHRO_REG (TPU_REG + 0x0E)
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123 #define TPU_DSP_PG (TPU_REG + 0x20)
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124
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125
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126
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127
153
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128
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129 /*
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130 * TPU control register bits
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131 */
153
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132 // GSM 1.5 : TPU bits changed
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133 //---------------------------------------
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134 #define TPU_CTRL_RESET 0x0001
153
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135 #define TSP_CTRL_RESET 0x0080
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136 #define TPU_CTRL_T_PAGE 0x0002
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137 #define TPU_CTRL_T_ENBL 0x0004
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138 #define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
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139 #define TPU_CTRL_SPI_RST 0x0080
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140 #define TPU_CTRL_WAIT 0x0200
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141 #define TPU_CTRL_CLK_EN 0x0400
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142 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
153
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143 #define TPU_CTRL_FULL_WRITE 0x0800
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144 #endif
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145
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146
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147
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148
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149 /*
153
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150 * TPU interrupt control register bits
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151 */
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152
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153
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154 /* WARNING BUG IN HYPERION. */
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155 /* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
153
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156
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157 #define TPU_INT_ITF_M 0x0001
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158 #define TPU_INT_ITP_M 0x0002
153
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159 #define TPU_INT_ITD_M 0x0004
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160 #define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
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161
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162 #define INT_FRAME 4 /* TPU frame interrupt */
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163 #define INT_PAGE 5 /* TPU page interrupt */
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164 #define INT_TSP 3 /* TSP interrupt */
153
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165
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166
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167
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168 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG==11))
153
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169 // BB signals connected to serial link1
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170 #define BULON 0x80 // bit6
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171 #define BULCAL 0x40 // bit5
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172 #define BULENA 0x20 // bit4
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173 #define BDLON 0x10 // bit3
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174 #define BDLCAL 0x08 // bit2
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175 #define BDLENA 0x04 // bit1
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176 #define STARTADC 0x02 // bit0
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177 #endif
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178
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179 #if (RF_FAM == 61)
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180 /* #define START_ADC 0x01 // TSPact 8 omaps00090550*/
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181 // TSPACT
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182 #define REG_SPI_ACT_U 0x07
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183 #define REG_SPI_ACT_L 0x06
153
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184
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185 #endif
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186 #define TPU_CTRL_TPU_IDLE 0x0100
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187
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188 /*
153
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189 * GSM RF programming times in quarter bits
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190 */
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191 /**************************************************************************/
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192 /**************************************************************************/
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193 /****************************** W A R N I N G !!! *************************/
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194 /******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/
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195 /****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/
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196 /**************************************************************************/
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197 /**************************************************************************/
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198
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199
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200 /**************************************/
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201 /* TPU Macros: prototypes functions */
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202 /**************************************/
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203 // TPU macros.
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204 //------------
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205 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
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206 void l1dmacro_init_hw (void);
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207 void l1dmacro_idle (void);
153
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208 void l1dmacro_rx_synth (SYS_UWORD16 radio_freq);
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209 void l1dmacro_tx_synth (SYS_UWORD16 radio_freq);
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210
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211
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212 #if (RF_FAM == 61)
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213 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna, UWORD8 if_ctl);
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214 #endif
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215 #if (RF_FAM != 61)
153
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216 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna);
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217 #endif
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218
153
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219 void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id);
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220 #if (L1_MADC_ON == 1)
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221 #if (RF_FAM == 61)
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222 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq,UWORD8 adc_active);
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223 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
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224 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq,UWORD8 adc_active);
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225 #endif
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226 #else
153
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227 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq);
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228 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq);
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229 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq);
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230 #endif
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231
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232 void l1dmacro_offset (UWORD32 offset_value,
153
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233 WORD32 relative_time);
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234 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
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235 #if (L1_MADC_ON == 1)
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236 #if (RF_FAM == 61)
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237 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
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238 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice
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239 #if (NEW_SNR_THRESHOLD == 1)
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240 ,UWORD8 saic_flag
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241 #endif /* NEW_SNR_THRESHOLD*/
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242 );
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243 #endif /* RF_FAM == 61*/
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244 #else /* L1_MADC_ON == 1*/
153
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245 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq);
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246 #if (RF_FAM == 61)
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247 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq, UWORD8 csf_filter_choice);
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248 #else
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249 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq);
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250 #endif // RF_FAM
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251 #endif // L1_MADC_ON
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252
153
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253 void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
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254 void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
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255
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256 #if (L1_MADC_ON == 1)
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257 #if (RF_FAM == 61)
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258 void l1dmacro_adc_read_tx (UWORD32 when, UWORD8 tx_up_state);
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259 #endif
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260 #endif
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261 #if (RF_FAM != 61)
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262 void l1dmacro_adc_read_tx (UWORD32 when);
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263 #endif
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264
153
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265 void l1dmacro_adc_read_rx (void);
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266
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267 #if (CODE_VERSION != SIMULATION)
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268 #if (L1_MADC_ON ==1)
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269 void l1dmacro_adc_read_rx_cs_mode0(void);
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270 #endif
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271 #endif
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272
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273
153
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274 void l1dmacro_set_frame_it (void);
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275 void l1dmacro_init_hw_light (void);
153
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276
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277 #if TESTMODE
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278 #if (L1_MADC_ON == 1)
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279 #if (RF_FAM == 61)
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280 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr,UWORD8 adc_active, UWORD8 csf_filter_choice
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281 #if (NEW_SNR_THRESHOLD == 1)
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282 ,UWORD8 saic_flag
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283 #endif /* NEW_SNR_THRESHOLD*/
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284 );
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285 #endif /* RF_FAM == 1*/
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286 #else /* L1_MADC_ON == 1*/
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287 #if (RF_RAM == 61)
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288 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 csf_filter_choice);
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289 #else
153
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290 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
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291 #endif /* RF_FAM */
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292 #endif /* L1_MADC_ON */
153
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293 void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
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294 void l1dmacro_stop_cont (void);
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295 #endif /* TESTMODE */
153
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296
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297 /*
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298 * TPU prototypes
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299 */
153
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300 void TP_PageIntHandler (void);
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301 void TP_FrameIntHandler (void);
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302 void TP_PageIntHandler (void);
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303 void TP_FrameIntHandler (void);
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304 void TPU_Reset(SYS_UWORD16 on);
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305 void TSP_Reset(SYS_UWORD16 on);
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306 void TPU_ClkEnable(SYS_UWORD16 on);
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307 void TP_Reset(SYS_UWORD16 on);
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308 void TP_Enable(SYS_UWORD16 on);
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309 BOOL TPU_check_IT_DSP(void);
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310
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311
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312 /*
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313 * TPUDRV global variables
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314 */
153
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315 #ifdef TPUDRV_C
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316 #define TP_GLOBAL
153
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317 #else
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318 #define TP_GLOBAL extern
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319 #endif
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320
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321 TP_GLOBAL volatile UWORD32 TP_PageInt;
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322 TP_GLOBAL volatile UWORD32 TP_FrameInt;