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annotate gsm-fw/bsp/oldint.S @ 875:dab341e172de

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fc-shell: sysprim sending (sp command) implemented
author Space Falcon <falcon@ivan.Harhan.ORG>
date Sat, 30 May 2015 07:41:23 +0000
parents afceeeb2cba1
children
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8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 /*
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2 * This module contains that part of TI's int.s (INT_Initialize) code
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3 * which does some entry-point initialization of a few Calypso registers.
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4 * The important part for us is getting rid of whatever PLL setup
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5 * may have been done by the BootROM-based process that got us loaded
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6 * and running - we need to do that before we can do our own setup.
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7 */
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8
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9 .code 32
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10 .text
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11
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12 #define CNTL_ARM_CLK_REG 0xFFFFFD00 // CNTL_ARM_CLK register address
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13 #define DPLL_CNTRL_REG 0xFFFF9800 // DPLL control register address
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14 #define EXTRA_CONTROL_REG 0xFFFFFB10 // Extra Control register CONF addr
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15 #define MPU_CTL_REG 0xFFFFFF08 // MPU_CTL register address
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16
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17 #define CNTL_ARM_CLK_RST 0x1081 // Init of CNTL_ARM_CLK register
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18
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19 // Use DPLL, Divide by 1
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20 #define DPLL_CONTROL_RST 0x2002 // Configure DPLL in default state
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21 #define DISABLE_DU_MASK 0x0800 // Mask to Disable the DU module
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22 #define ENABLE_DU_MASK 0xF7FF // Mask to Enable the DU module
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23 #define MPU_CTL_RST 0x0000 // Reset value of MPU_CTL register
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24 // - All protections disabled
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25
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26 .globl freecalypso_disable_bootrom_pll
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27 freecalypso_disable_bootrom_pll:
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28 @
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29 @ Configure DPLL register with reset value
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30 @
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31 ldr r1,=DPLL_CNTRL_REG @ Load address of DPLL register in R1
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32 ldrh r2,=DPLL_CONTROL_RST @ Load DPLL reset value in R2
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33 strh r2,[r1] @ Store DPLL reset value in DPLL register
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34
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35 @
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36 @ Wait that DPLL goes in BYPASS mode
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37 @
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38 Wait_DPLL_Bypass:
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39 ldr r2,[r1] @ Load DPLL register
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40 and r2,r2,#1 @ Perform a mask on bit 0
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41 cmp r2,#1 @ Compare DPLL lock bit
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42 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
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43
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44 @
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45 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
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46 @ generate ARM clock with division factor of 1.
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47 @
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48 ldr r1,=CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
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49 ldrh r2,=CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
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50 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
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51
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52 @
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53 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
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54 @
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55 ldr r1,=EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
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56 @ ldrh r2,=DISABLE_DU_MASK @ Load mask to write in Extra Control register CONF
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57 ldrh r2,=ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
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58 ldrh r0,[r1] @ Load Extra Control register CONF in r0
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59 @ orr r0,r0,r2 @ Disable DU module
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60 and r0,r0,r2 @ Enable DU module
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61 strh r0,[r1] @ Store configuration in Extra Control register CONF
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62
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63 @
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64 @ Disable all MPU protections
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65 @
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66 ldr r1,=MPU_CTL_REG @ Load address of MPU_CTL register
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67 ldrh r2,=MPU_CTL_RST @ Load reset value of MPU_CTL register
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68 strh r2,[r1] @ Store reset value of MPU_CTL register
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69
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70 bx lr