FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/L1/audio_include/l1audio_const.h @ 691:e7b45d295580
cc_em.c compiles
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Tue, 30 Sep 2014 01:29:41 +0000 |
parents | 45bf440cc677 |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1AUDIO_CONST.H |
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4 * |
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5 * Filename l1audio_const.h |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 #if (AUDIO_TASK == 1) |
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11 |
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12 // DRC API base address |
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13 #define C_DRC_API_BASE_ADDRESS 0x161E |
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14 |
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15 //---------------------------------------- |
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16 // LAYER 1 Synchronous audio process name. |
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17 //---------------------------------------- |
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18 |
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19 #define NBR_AUDIO_MANAGER 37 // Number of L1S audio managers |
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20 |
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21 #define L1S_KEYBEEP_STATE 0 // l1s_keybeep_manager() |
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22 #define L1S_TONE_STATE 1 // l1s_tone_manager() |
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23 #define L1S_MELODY0_STATE 2 // l1s_melody0_manager() |
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24 #define L1S_MELODY1_STATE 3 // l1s_melody1_manager() |
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25 #define L1S_VM_PLAY_STATE 4 // l1s_vm_play_manager() |
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26 #define L1S_VM_RECORD_STATE 5 // l1s_vm_record_manager() |
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27 #define L1S_TONE_UL_STATE 6 // l1s_tone_ul_manager() |
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28 #define L1S_SR_ENROLL_STATE 7 // l1s_sr_enroll_manager() |
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29 #define L1S_SR_UPDATE_STATE 8 // l1s_sr_update_manager() |
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30 #define L1S_SR_RECO_STATE 9 // l1s_sr_reco_manager() |
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31 #define L1S_SR_PROCESSING_STATE 10 // l1s_sr_processing_manager() |
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32 #define L1S_SR_SPEECH_STATE 11 // l1s_sr_speech_manager() |
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33 #define L1S_AEC_STATE 12 // l1s_aec_manager() |
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34 #define L1S_AUDIO_MODE_STATE 13 // l1s_audio_mode_manager() |
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35 #define L1S_MELODY0_E2_STATE 14 // l1s_melody0_e2_manager() |
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36 #define L1S_MELODY1_E2_STATE 15 // l1s_melody1_e2_manager() |
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37 #define L1S_VM_AMR_PLAY_STATE 16 // l1s_vm_amr_play_manager() |
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38 #define L1S_VM_AMR_RECORD_STATE 17 // l1s_vm_amr_record_manager() |
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39 #define L1S_CPORT_STATE 18 // l1s_cport_manager() |
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40 #define L1S_AUDIO_ONOFF_STATE 19 // l1s_audio_onoff_manager() |
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41 #define L1S_STEREOPATH_DRV_STATE 20 // l1s_stereopath_drv_manager() |
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42 #define L1S_MP3_STATE 21 // l1s_mp3_manager() |
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43 #define L1S_ANR_STATE 22 // l1s_anr_manager() |
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44 #define L1S_IIR_STATE 23 // l1s_iir_manager() |
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45 #define L1S_LIMITER_STATE 24 // l1s_limiter_manager() |
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46 #define L1S_ES_STATE 25 // l1s_es_manager() |
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47 #define L1S_MIDI_STATE 26 // l1s_midi_manager() |
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48 #define L1S_AGC_UL_STATE 27 // l1s_agc_ul_manager() |
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49 #define L1S_AGC_DL_STATE 28 // l1s_agc_dl_manager() |
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50 #define L1S_WCM_STATE 29 // l1s_wcm_manager() |
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51 #define L1S_DRC_STATE 30 // l1s_drc_manager() |
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52 #if (L1_AAC == 1) |
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53 |
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54 //added from e-sample for AAC |
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55 #define L1S_AAC_STATE 31 // l1s_aac_manager() |
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56 #endif |
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57 #if (L1_AUDIO_MCU_ONOFF == 1) |
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58 #define L1S_AUDIO_UL_ONOFF_STATE 32 // l1s_audio_ul_onoff_manager() |
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59 #define L1S_AUDIO_DL_ONOFF_STATE 33 // l1s_audio_dl_onoff_manager() |
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60 #endif |
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61 #define L1S_PCM_DOWNLOAD_STATE 34 // l1s_pcm_download_manager() |
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62 #define L1S_PCM_UPLOAD_STATE 35 // l1s_pcm_upload_manager() |
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63 #define L1S_FIR_STATE 36 // l1s_fir_manager() |
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64 |
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65 |
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66 //---------------------------------------- |
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67 // MCU<->DSP communication bit field. |
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68 //---------------------------------------- |
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69 |
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70 // bit in d_tch_mode for audio features |
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71 #define B_VOICE_MEMO_DTX (TRUE_L << 5) |
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72 #if (DSP >= 34) |
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73 #define B_VM_VOCODER_SELECT (TRUE_L << 6) |
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74 #endif |
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75 |
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76 // bits in d_toneskb_status |
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77 #define B_TONE (TRUE_L << 0) // Indicate if the DSP tone task is running |
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78 #define B_KEYBEEP (TRUE_L << 1) // Indicate if the DSP Keybeep task is running |
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79 #define B_VM_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech task is running |
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80 #define B_VM_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing task is running |
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81 #define B_VM_AMR_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech amr task is running |
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82 #define B_VM_AMR_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing amr task is running |
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83 #define B_SR_ENROLL_TASK (TRUE_L << 4) // Indicate if the DSP enroll task is running |
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84 #define B_SR_UPDATE_TASK (TRUE_L << 5) // Indicate if the DSP update task is running |
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85 #define B_SR_RECO_TASK (TRUE_L << 6) // Indicate if the DSP reco task is running |
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86 #define B_SR_PROCESSING_TASK (TRUE_L << 7) // Indicate if the DSP processing task is running |
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87 #define B_SR_ALIGNMENT_TASK (TRUE_L << 8) // Indicate if the DSP alignment task is running |
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88 #define B_IT_COM_REQ (TRUE_L << 9) // Indicate that the DSP requests an IT com for the next TDMA |
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89 #define B_AUDIO_ON_STATUS (TRUE_L << 14) // Set to 1 if DSP doesn'tpower OFF audio ABB if no DSP audio activity |
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90 |
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91 #if(L1_PCM_EXTRACTION) |
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92 #define B_PCM_UPLOAD_ON_GOING (TRUE_L << 4) |
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93 #define B_PCM_DOWNLOAD_ON_GOING (TRUE_L << 5) |
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94 #endif |
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95 |
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96 // bits in d_toneskb_init |
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97 #define B_VM_RECORD_START (TRUE_L << 2) // Start the DSP voice memo recording task |
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98 #define B_VM_RECORD_STOP (TRUE_L << 3) // Stop the DSP voice memo recording task |
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99 #define B_VM_PLAY_START (TRUE_L << 4) // Start the DSP voice memo playing task |
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100 #define B_VM_PLAY_STOP (TRUE_L << 5) // Stop the DSP voice memo playing task |
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101 #define B_VM_TONE_UL (TRUE_L << 6) // Generate the tone on the UL path |
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102 #define B_VM_AMR_RECORD_START (TRUE_L << 2)// Start the DSP voice memo amr recording task |
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103 #define B_VM_AMR_RECORD_STOP (TRUE_L << 3)// Stop the DSP voice memo amr recording task |
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104 #define B_VM_AMR_PLAY_START (TRUE_L << 4)// Start the DSP voice memo amr playing task |
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105 #define B_VM_AMR_PLAY_STOP (TRUE_L << 5)// Stop the DSP voice memo amr playing task |
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106 #define B_SR_ENROLL (TRUE_L << 7) // Start the DSP speech reco enroll task |
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107 #define B_SR_UPDATE (TRUE_L << 8) // Start the DSP speech reco update task |
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108 #define B_SR_RECO (TRUE_L << 9) // Start the DSP speech reco task |
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109 #define B_SR_PROCESSING (TRUE_L << 10) // Start the DSP speech reco processing task |
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110 #define B_SR_STOP (TRUE_L << 11) // Stop the current DSP speech reco task |
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111 |
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112 #define B_MELO (TRUE_L << 13) // Start the DSP melody module if it's not started |
603
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113 #define B_AUDIO_ON_START (TRUE_L << 14) // Use to start ABB audio and to not stop it when |
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114 // no audio activity on DSP side |
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115 #define B_AUDIO_OFF_STOP (TRUE_L << 15) // Use to stop ABB audio when no audio activity |
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116 |
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117 #if(L1_PCM_EXTRACTION) |
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118 #define B_PCM_UPLOAD_START (TRUE_L << 7) |
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119 #define B_PCM_UPLOAD_STOP (TRUE_L << 8) |
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120 #define B_PCM_DOWNLOAD_START (TRUE_L << 9) |
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121 #define B_PCM_DOWNLOAD_STOP (TRUE_L << 10) |
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122 #endif |
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123 |
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124 #if (L1_CPORT == 1) |
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125 //---------------------------------------- |
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126 // C_PORT constant. |
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127 //---------------------------------------- |
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128 |
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129 #define CPORT_READ_FLAG_OFFSET 11 // offset in configuration field of the "read register" bit |
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130 #define CPORT_REG_NB_OFFSET 12 // offset in configuration field of the register number |
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131 #define CPORT_READ_MASK 0xF800 // mask to get the read flag and the read reg id in the d_cport_status field |
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132 |
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133 // write register defines |
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134 #define CPORT_W_NONE 0 // do not write anything |
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135 #define CPORT_W_CTRL 1 // write CTRL, set bit 0 of configuration to 1 |
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136 #define CPORT_W_CPCFR1 1 << 1 // write CPCFR1, set bit 1 of configuration to 1 |
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137 #define CPORT_W_CPCFR2 1 << 2 // write CPCFR2, set bit 2 of configuration to 1 |
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138 #define CPORT_W_CPCFR3 1 << 3 // write CPCFR3, set bit 3 of configuration to 1 |
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139 #define CPORT_W_CPCFR4 1 << 4 // write CPCFR4, set bit 4 of configuration to 1 |
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140 #define CPORT_W_CPTCTL 1 << 5 // write CPTCTL, set bit 5 of configuration to 1 |
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141 #define CPORT_W_CPTTADDR 1 << 6 // write CPTTADDR, set bit 6 of configuration to 1 |
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142 #define CPORT_W_CPTDAT 1 << 7 // write CPTDAT, set bit 7 of configuration to 1 |
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143 #define CPORT_W_CPTVS 1 << 8 // write CPTVS, set bit 8 of configuration to 1 |
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144 |
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145 // read register defines |
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146 #define CPORT_R_NONE 0 // do not read anything |
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147 // for each of the following defines, set read flag (bit 11) to 1 and set reg_nb (bits 12..15) |
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148 #define CPORT_R_CTRL (0 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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149 #define CPORT_R_CPCFR1 (1 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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150 #define CPORT_R_CPCFR2 (2 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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151 #define CPORT_R_CPCFR3 (3 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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152 #define CPORT_R_CPCFR4 (4 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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153 #define CPORT_R_CPTCTL (5 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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154 #define CPORT_R_CPTTADDR (6 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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155 #define CPORT_R_CPTDAT (7 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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156 #define CPORT_R_CPTVS (8 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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157 #define CPORT_R_STATUS (9 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) |
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158 |
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159 #endif |
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160 |
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161 |
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162 #if (MELODY_E1) |
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163 //---------------------------------------- |
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164 // Melody constant. |
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165 //---------------------------------------- |
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166 |
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167 // Word to indicate that the oscillator must be stopped ASAP |
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168 #define SC_END_OSCILLATOR_MASK 0xfffe |
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169 |
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170 // Description of the ml_ocscil_x field (x= 0...SC_NUMBER_OSCILLATOR) |
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171 #define SC_MELO_OSCILLATOR_USED_MASK 0xff00 |
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172 #define SC_MELO_OSCILLATOR_USED_SHIFT SC_NUMBER_OSCILLATOR |
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173 |
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174 // Description of the ml_time_offset field |
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175 #define SC_MELO_TIME_OFFSET_MASK 0x00ff |
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176 #define SC_MELO_TIME_OFFSET_SHIFT 0 |
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177 |
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178 // Description of the ml_load1 bit |
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179 #define SC_MELO_LOAD1_MASK 0x0010 |
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180 #define SC_MELO_LOAD1_SHIFT 4 |
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181 |
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182 // Description of the ml_load2 bit |
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183 #define SC_MELO_LOAD2_MASK 0x0020 |
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184 #define SC_MELO_LOAD2_SHIFT 5 |
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185 |
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186 // Description of the ml_synchro bit |
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187 #define SC_MELO_SYNCHRO_MASK 0x0001 |
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188 #define SC_MELO_SYNCHRO_SHIFT 0 |
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189 |
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190 // Description of the ml_length field |
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191 #define SC_MELO_LENGTH_MASK 0xffc0 |
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192 #define SC_MELO_LENGTH_SHIFT 6 |
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193 #endif // MELODY_E1 |
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194 |
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195 #if (VOICE_MEMO) || (SPEECH_RECO) |
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196 //---------------------------------------- |
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197 // Voice memo constant. |
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198 //---------------------------------------- |
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199 |
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200 // Communication DSP<->MCU via the a_du_x buffer: |
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201 |
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202 // Mask for the bit to indicate: |
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203 // in VM play: if the DSP requests a new block |
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204 // in VM record: if the DSP has a new block |
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205 #define B_BLOCK_READY (TRUE_L<<10) |
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206 |
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207 // Mask for the bit of the a_du_x buffer to indicate if the block is the speech or noise |
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208 #define B_VM_SPEECH (TRUE_L<<15) |
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209 |
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210 // Size of the a_du_x buffer when the sample is a noise: |
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211 #define SC_VM_NOISE_SAMPLE 1 |
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212 |
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213 // Size of the a_du_x buffer when the sample is a speech: |
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214 #define SC_VM_SPEECH_SAMPLE 20 |
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215 #endif // VOICE_MEMO || SPEECH_RECO |
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216 |
603
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217 #if (L1_PCM_EXTRACTION) |
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218 #define B_PCM_DOWNLOAD_READY (TRUE_L << 0) |
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219 #define B_PCM_UPLOAD_READY (TRUE_L << 0) |
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220 #define SC_PCM_DOWNLOAD_SAMPLE 160 |
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221 #define SC_PCM_UPLOAD_SAMPLE 160 |
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222 #define B_PCM_UPLOAD_ERROR (TRUE_L << 0) |
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223 #define B_PCM_DOWNLOAD_ERROR (TRUE_L << 1) |
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224 #endif /* L1_PCM_EXTRACTION */ |
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225 |
519
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226 #if (L1_VOICE_MEMO_AMR) |
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227 //---------------------------------------- |
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228 // Voice memo amr constant. |
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229 //---------------------------------------- |
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230 |
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231 #define SC_VM_AMR_HEADER_SIZE 1 |
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232 |
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233 // Communication DSP<->MCU via the a_du_x buffer: |
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234 #define SC_RX_TX_TYPE_MASK (7<<3) |
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235 |
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236 // Communication DSP<->MCU via d_amms_ul_voc and b_amms_channel_type |
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237 #define SC_CHAN_TYPE_MASK 7 |
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238 |
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239 // RX_TYPE or TX_TYPE (See 06.93) |
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240 #define SC_VM_AMR_RXTX_SPEECH_GOOD (0<<3) |
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241 #define SC_VM_AMR_RXTX_SPEECH_DEGRADED (1<<3) |
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242 #define SC_VM_AMR_RXTX_ONSET (2<<3) |
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243 #define SC_VM_AMR_RXTX_SPEECH_BAD (3<<3) |
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244 #define SC_VM_AMR_RXTX_SID_FIRST (4<<3) |
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245 #define SC_VM_AMR_RXTX_SID_UPDATE (5<<3) |
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246 #define SC_VM_AMR_RXTX_SID_BAD (6<<3) |
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247 #define SC_VM_AMR_RXTX_NO_DATA (7<<3) |
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248 |
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249 // sample type for ONSET insertion in NO_SPEECH to SPEECH transition |
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250 #define SC_VM_AMR_SPEECH 0 |
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251 #define SC_VM_AMR_NOISE 1 |
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252 #define SC_VM_AMR_NO_DATA 2 |
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253 #define SC_VM_AMR_ONSET 3 |
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254 |
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255 // Speech channel type |
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256 #define SC_VM_AMR_SPEECH_475 0 |
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257 #define SC_VM_AMR_SPEECH_515 1 |
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258 #define SC_VM_AMR_SPEECH_59 2 |
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259 #define SC_VM_AMR_SPEECH_67 3 |
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260 #define SC_VM_AMR_SPEECH_74 4 |
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261 #define SC_VM_AMR_SPEECH_795 5 |
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262 #define SC_VM_AMR_SPEECH_102 6 |
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263 #define SC_VM_AMR_SPEECH_122 7 |
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264 |
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265 // Size of data bits in the a_du_x buffer when the sample is SPEECH |
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266 // a_du_x buffer contains header + 2 non-used words after header + data_bits => recorded size is DATA_SIZE + 1 |
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267 #define SC_VM_AMR_SPEECH_475_DATA_SIZE 12 |
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268 #define SC_VM_AMR_SPEECH_515_DATA_SIZE 13 |
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269 #define SC_VM_AMR_SPEECH_59_DATA_SIZE 15 |
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270 #define SC_VM_AMR_SPEECH_67_DATA_SIZE 17 |
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271 #define SC_VM_AMR_SPEECH_74_DATA_SIZE 19 |
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272 #define SC_VM_AMR_SPEECH_795_DATA_SIZE 20 |
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273 #define SC_VM_AMR_SPEECH_102_DATA_SIZE 26 |
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274 #define SC_VM_AMR_SPEECH_122_DATA_SIZE 31 |
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275 |
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276 // Size of the a_du_x buffer when the sample is SID_FIRST: |
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277 #define SC_VM_AMR_SID_FIRST_DATA_SIZE 5 |
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278 |
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279 // Size of the a_du_x buffer when the sample is SID_UPDATE: |
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280 #define SC_VM_AMR_SID_UPDATE_DATA_SIZE 5 |
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281 |
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282 // Size of the a_du_x buffer when the sample is SID_BAD: |
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283 #define SC_VM_AMR_SID_BAD_DATA_SIZE 5 |
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284 |
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285 // Size of the a_du_x buffer when the sample is NO_DATA: |
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286 #define SC_VM_AMR_NO_DATA_DATA_SIZE 0 |
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287 |
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288 // Size of the a_du_x buffer when the sample is ONSET: |
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289 #define SC_VM_AMR_ONSET_DATA_SIZE 0 |
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290 |
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291 #endif // L1_VOICE_MEMO_AMR |
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292 |
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293 #if (SPEECH_RECO) |
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294 //---------------------------------------- |
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295 // Speech recognition constant. |
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296 //---------------------------------------- |
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297 |
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298 // d_sr_status bit field |
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299 #define B_BAD_ACQUISITION (TRUE_L << 8) |
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300 #define B_GOOD_ACQUISITION (TRUE_L << 9) |
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301 #define B_BAD_UPDATE (TRUE_L << 10) |
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302 #define B_GOOD_UPDATE (TRUE_L << 11) |
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303 |
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304 // d_sr_status VAD indication |
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305 #define SC_SR_WORD_MASK 0x00FF |
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306 #define SC_SR_WORD_SEARCHING 0 |
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307 #define SC_SR_WORD_BEGINNING 1 |
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308 #define SC_SR_WORD_ON_GOING 2 |
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309 #define SC_SR_WORD_ENDING 3 |
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310 #define SC_SR_WORD_DONE 4 |
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311 |
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312 #endif // SPEECH_RECO |
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313 |
603
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314 #if (L1_AEC == 1) |
519
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315 #define B_AEC_ACK (TRUE_L << 0) // Bit set by the MCU to indicate a new AEC settings and |
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316 // clear by the DSP to confirm the new settings. |
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317 #if (L1_NEW_AEC) |
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318 #define B_AEC_VISIBILITY (TRUE_L << 9) // Bit set by the MCU to have internal output values of AEC copied in API |
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319 #define SC_AEC_VISIBILITY_SHIFT (9) |
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320 #endif |
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321 |
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322 #endif |
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323 |
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324 |
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325 #if (W_A_DSP_SR_BGD) |
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326 #define C_BGD_RECOGN 5 // TEMPORARY: DSP Background recognition task code (also used for bitmaps). |
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327 #define C_BGD_ALIGN 6 // TEMPORARY: DSP Background alignement |
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328 // bits in d_gsm_bgd_mgt - background task management |
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329 #define B_DSPBGD_RECO 1 // start of reco in dsp background |
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330 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background |
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331 #endif |
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332 #if (AUDIO_MODE) |
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333 #define B_GSM_ONLY ((TRUE_L << 13) | (TRUE_L << 11)) // GSM normal mode |
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334 #define B_BT_CORDLESS (TRUE_L << 12) // Bluetooth cordless mode |
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335 #define B_BT_HEADSET (TRUE_L << 14) // Bluetooth headset mode |
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336 #endif |
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337 |
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338 #define SC_AUDIO_MCU_API_BEGIN_ADDRESS (0xFFD00000) // Start address of the API memory in MCU side |
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339 #define SC_AUDIO_DSP_API_BEGIN_ADDRESS (0x0800) // Start address o fthe API memory in DSP side |
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340 |
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341 #if (MELODY_E2) |
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342 // Number of oscillator available in the melody E2 |
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343 #define SC_MELODY_E2_NUMBER_OF_OSCILLATOR (16) |
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344 |
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345 // Code of extension for data=time |
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346 #define SC_TIME_CODE_OF_EXTENSION (1) |
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347 |
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348 // Position of the GlobalTimeFactor parameter |
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349 #define SC_MELODY_E2_GLOBALTIMEFACTOR_MASK (0xFF) |
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350 #define SC_MELODY_E2_GLOBALTIMEFACTOR_SHIFT (0) |
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351 |
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352 // Position of the Number of instrument parameter |
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353 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_MASK (0xFF) |
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354 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_SHIFT (0) |
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355 |
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356 // Position of the extension flag |
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357 #define SC_MELODY_E2_EXTENSION_FLAG_MASK (0x80) |
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358 #define SC_MELODY_E2_EXTENSION_FLAG_SHIFT (7) |
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359 |
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360 // Position of the code of extension |
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361 #define SC_MELODY_E2_CODE_OF_EXTENSION_MASK (0x70) |
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362 #define SC_MELODY_E2_CODE_OF_EXTENSION_SHIFT (4) |
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363 |
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364 // Position of data time |
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365 #define SC_MELODY_E2_DATA_TIME_MSB_MASK (0x07) |
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366 #define SC_MELODY_E2_DATA_TIME_MSB_SHIFT (0) |
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367 |
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368 // Position of data time |
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369 #define SC_MELODY_E2_DATA_TIME_LSB_MASK (0xFF00) |
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370 #define SC_MELODY_E2_DATA_TIME_LSB_SHIFT (8) |
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371 |
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372 // Position of the Delta Time |
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373 #define SC_MELODY_E2_DELTA_TIME_MASK (0x7F) |
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374 #define SC_MELODY_E2_DELTA_TIME_SHIFT (0) |
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375 |
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376 // Mask of the semaphore |
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377 #define SC_MELODY_E2_SEMAPHORE_MASK (0x0001) |
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378 |
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379 // Maximum size of the header of the melody E2 |
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380 #define SC_MELODY_E2_MAXIMUM_HEADER_SIZE (3 + SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT) |
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381 |
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382 // Maximum number of extension |
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383 #define SC_MELODY_E2_MAXIMUM_NUMBER_OF_EXTENSION (2) |
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384 #endif // MELODY_E2 |
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385 |
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386 // Selection of the melody format |
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387 #define NO_MELODY_SELECTED (0) |
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388 #define MELODY_E0_SELECTED (1) |
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389 #define MELODY_E1_SELECTED (2) |
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390 #define MELODY_E2_SELECTED (3) |
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391 |
603
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392 #if (L1_STEREOPATH == 1) |
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393 // configuration |
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394 #define AUDIO_SP_SELF_CONF 0 |
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395 #define AUDIO_SP_MIDI_CONF 1 |
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396 #define AUDIO_SP_MP3_CONF 2 |
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397 #define AUDIO_SP_EXTAUDIO_CONF 3 |
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398 |
604
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399 #if (ANALOG == 3) |
603
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400 // sampling frequency |
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401 #define AUDIO_SP_FREQ_8 7 |
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402 #define AUDIO_SP_FREQ_11 6 |
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403 #define AUDIO_SP_FREQ_16 5 |
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404 #define AUDIO_SP_FREQ_22 4 |
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405 #define AUDIO_SP_FREQ_32 3 |
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406 #define AUDIO_SP_FREQ_44 2 |
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407 #define AUDIO_SP_FREQ_48 0 |
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408 #endif |
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409 |
604
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410 #if (ANALOG == 11 || CODE_VERSION == SIMULATION) |
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411 // sampling frequency index for Triton. This would be set in the |
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412 //SRW[0:3] bits of the CTRL5 register. |
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413 #define AUDIO_SP_FREQ_8 0 |
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414 #define AUDIO_SP_FREQ_11 1 |
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415 #define AUDIO_SP_FREQ_12 2 |
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416 #define AUDIO_SP_FREQ_16 3 |
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417 #define AUDIO_SP_FREQ_22 4 |
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418 #define AUDIO_SP_FREQ_24 5 |
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419 #define AUDIO_SP_FREQ_32 6 |
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420 #define AUDIO_SP_FREQ_44 7 |
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421 #define AUDIO_SP_FREQ_48 8 |
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422 #endif |
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423 |
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424 // DMA allocation |
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425 #define AUDIO_SP_DMA_ALLOC_MCU 0 |
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426 #define AUDIO_SP_DMA_ALLOC_DSP 1 |
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427 |
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428 // Data type |
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429 #define AUDIO_SP_DATA_S8 0 |
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430 #define AUDIO_SP_DATA_S16 1 |
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431 #define AUDIO_SP_DATA_S32 2 |
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432 |
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433 // Source port |
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434 #define AUDIO_SP_SOURCE_IMIF 0 |
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435 #define AUDIO_SP_SOURCE_API 2 |
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436 #if (CHIPSET == 15) |
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437 //In Locosto, EMIF is also a source port for the audio |
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438 #define AUDIO_SP_SOURCE_EMIF 4 |
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439 #endif |
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440 |
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441 // output type |
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442 #define AUDIO_SP_MONO_OUTPUT 0 |
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443 #define AUDIO_SP_STEREO_OUTPUT 1 |
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444 |
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445 // feature identifier |
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446 #define AUDIO_SP_MIDI_ID 0 |
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447 #define AUDIO_SP_EXT_AUDIO_ID 1 |
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448 #define AUDIO_SP_MP3_ID 2 |
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449 #define AUDIO_SP_TESTS_ID 3 |
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450 #if (L1_AAC == 1) |
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451 #define AUDIO_SP_AAC_ID 4 //added for AAC |
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452 #endif |
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453 |
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454 // Pattern |
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455 #define AUDIO_SP_SILENCE_PATTERN 0 |
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456 #define AUDIO_SP_SINUS1_PATTERN 1 |
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457 #define AUDIO_SP_SINUS2_PATTERN 2 |
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458 #define AUDIO_SP_SINUS3_PATTERN 3 |
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459 |
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460 #endif |
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461 |
519
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462 #endif // AUDIO_TASK |
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463 |
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464 #if (DSP == 17) || (DSP == 32) |
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465 #define B_FIR_START (TRUE_L << 0) // Bit set by the MCU to start the FIR task for the DSP code 32 and 17. |
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466 #endif |
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467 |
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468 #define B_FIR_LOOP (TRUE_L << 1) // Bit set by the MCU to close the loop between the audio UL and DL path. |
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469 // This features is used to find the FIR coefficient. |
603
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470 |
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471 /*************************************/ |
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472 /* ACOUSTIC interface */ |
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473 /*************************************/ |
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474 |
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475 /* Control values */ |
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476 /*----------------*/ |
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477 |
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478 #define B_ANR_ENABLE (TRUE_L << 0) |
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479 #define B_ANR_DISABLE (TRUE_L << 1) |
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480 #define B_ANR_FULL_UPDATE (TRUE_L << 2) |
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481 |
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482 #define B_IIR_ENABLE (TRUE_L << 0) |
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483 #define B_IIR_DISABLE (TRUE_L << 1) |
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484 #define B_IIR_FULL_UPDATE (TRUE_L << 2) |
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485 |
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486 #define B_AGC_ENABLE (TRUE_L << 0) |
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487 #define B_AGC_DISABLE (TRUE_L << 1) |
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488 #define B_AGC_FULL_UPDATE (TRUE_L << 2) |
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489 |
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490 #define B_WCM_ENABLE (TRUE_L << 0) |
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491 #define B_WCM_DISABLE (TRUE_L << 1) |
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492 #define B_WCM_FULL_UPDATE (TRUE_L << 2) |
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493 |
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494 #if (L1_DRC == 1) |
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495 #define DRC_LPF_LENGTH 17 |
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496 #define DRC_BPF_LENGTH 17 |
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497 #endif |
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498 |
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499 #define B_DRC_ENABLE (TRUE_L << 0) |
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500 #define B_DRC_DISABLE (TRUE_L << 1) |
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501 #define B_DRC_FULL_UPDATE (TRUE_L << 2) |
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502 |
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503 #define B_LIM_ENABLE (TRUE_L << 0) |
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504 #define B_LIM_DISABLE (TRUE_L << 1) |
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505 #define B_LIM_FULL_UPDATE (TRUE_L << 2) |
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506 #define B_LIM_UPDATE (TRUE_L << 3) |
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507 |
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508 #define B_ES_ENABLE (TRUE_L << 0) |
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509 #define B_ES_DISABLE (TRUE_L << 1) |
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510 #define B_ES_FULL_UPDATE (TRUE_L << 2) |
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511 |
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512 #if (L1_IIR == 2) |
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513 #define IIR_4X_ORDER_OF_SECTION 2 |
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514 #define IIR_4X_FIR_MAX_LENGTH 40 |
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515 #endif |
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516 |
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517 #if (L1_WCM == 1) |
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518 #define WCM_1X_GAIN_TABLE_LENGTH 16 |
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519 #endif |
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520 |
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521 /* d_aqi_status bits */ |
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522 /*-------------------*/ |
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523 #if (DSP == 38) || (DSP == 39) |
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524 #define B_DRC_DL_STATE (TRUE_L << 3) |
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525 #define B_IIR_DL_STATE (TRUE_L << 4) |
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526 #define B_LIM_STATE (TRUE_L << 5) |
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527 #define B_AGC_DL_STATE (TRUE_L << 6) |
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528 #define B_AEC_STATE (TRUE_L << 11) |
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529 #define B_ANR_UL_STATE (TRUE_L << 12) |
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530 #define B_ES_STATE (TRUE_L << 13) |
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531 #define B_AGC_UL_STATE (TRUE_L << 14) |
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532 #else |
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533 #define B_IIR_STATE (TRUE_L << 4) |
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534 #define B_LIM_STATE (TRUE_L << 5) |
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535 #define B_ANR_STATE (TRUE_L << 12) |
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536 #define B_ES_STATE (TRUE_L << 13) |
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537 #endif |
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538 |
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539 /* d_audio_apps_status bits */ |
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540 /*-------------------*/ |
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541 #if (DSP == 38) || (DSP == 39) |
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542 #define B_WCM_STATE (TRUE_L << 0) |
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543 #endif |
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544 |
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545 /*****************/ |
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546 /* ANR constants */ |
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547 /*****************/ |
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548 #if (L1_ANR == 1) |
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549 #define C_ANR_VAD_THR 0x1333 |
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550 #define C_ANR_GAMMA_SLOW 0x7F1B |
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551 #define C_ANR_GAMMA_FAST 0x75C3 |
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552 #define C_ANR_GAMMA_GAIN_SLOW 28836 |
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553 #define C_ANR_GAMMA_GAIN_FAST 32113 |
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554 #define C_ANR_THR2 0x01E0 |
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555 #define C_ANR_THR4 0x03DE |
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556 #define C_ANR_THR5 0x012C |
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557 #define C_ANR_MEAN_RATIO_THR1 10000 |
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558 #define C_ANR_MEAN_RATIO_THR2 6000 |
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559 #define C_ANR_MEAN_RATIO_THR3 5000 |
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560 #define C_ANR_MEAN_RATIO_THR4 4000 |
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561 #endif |
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562 |
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563 |
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564 #if (L1_ES == 1) |
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565 |
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566 /*******************/ |
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567 /* ES constants */ |
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568 /*******************/ |
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569 |
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570 // ES custom mode |
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571 #define ES_CUSTOM_PARAM 0xFF |
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572 |
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573 // ES mode definition |
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574 #define B_ES_UL (0x1 << 0) // ES UL enable |
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575 #define B_ES_DL (0x1 << 1) // ES DL enable |
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576 #define B_ES_CNG (0x1 << 2) // CNG enable |
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577 #define B_ES_NSF (0x1 << 3) // NSF enable |
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578 #define B_ES_ALS_UL (0x1 << 4) // ALS UL enable |
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579 #define B_ES_ALS_DL (0x1 << 5) // ALS DL enable |
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580 |
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581 // ES parameter values |
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582 #define C_ES_GAIN_DL_OFF 0x0 |
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583 #define C_ES_GAIN_UL_1_OFF 0x0 |
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584 #define C_ES_GAIN_UL_2_OFF 0x0 |
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585 |
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586 #define C_ES_TCL_M23DB 0x005E // ref. -23dB |
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587 #define C_ES_TCL_M6DB 0x0176 // ref. -6dB |
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588 #define C_ES_TCL_M3DB 0x02EA // ref. -6dB |
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589 #define C_ES_TCL_0DB 0x05D1 // ref. 0dB |
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590 #define C_ES_TCL_4DB 0x0E9D // ref. 4dB |
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591 #define C_ES_TCL_6DB 0x1729 // ref. 6dB |
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592 #define C_ES_TCL_10DB 0x3A2F // ref. 10dB |
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593 #define C_ES_TCL_12DB 0x5C36 // ref. 12dB |
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594 #define C_ES_TCL_B3_FE_LS 0x0004 // ref. -10dB |
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595 #define C_ES_TCL_B3_DT_LS 0x0001 // ref. -16dB |
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596 #define C_ES_TCL_B3_FE_NS 0x000F // ref. -10dB |
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597 #define C_ES_TCL_B3_DT_NS 0x0004 // ref. -16dB |
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598 #define C_ES_TCL_B3_NE 0x000F // ref. 0dB |
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599 |
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600 #define C_ES_TCL_FE_0 0x05D1 // ref. 0dB |
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601 #define C_ES_TCL_DT_0 0x05D1 // ref. 0dB |
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602 #define C_ES_TCL_NE_0 0x05D1 // ref. 0dB |
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603 |
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604 #define C_ES_TCL_LOUD 0x00BF // ref. 70dB |
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605 |
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606 #define C_ES_SW_CNT 5 // ref. switching time 100ms |
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607 #define C_ES_DT_CNT 5 // ref. double-talk time 100ms |
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608 |
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609 #define C_ES_HG_CNT_1 8 // ref. hangover time 150ms, A_S(IDLE) = -3dB |
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610 #define C_ES_HG_CNT_1A 8 // ref. hangover time 150ms, A_S(IDLE) = -3dB |
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611 #define C_ES_HG_CNT_2A 10 // ref. hangover time 200ms, A_S(IDLE) = -3dB |
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612 #define C_ES_HG_CNT_2B 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB |
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613 #define C_ES_HG_CNT_2C 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB |
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614 #define C_ES_HG_CNT_2C_IDLE 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB |
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615 #define C_ES_HG_CNT_3 20 // ref. hangover time 400ms |
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616 |
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617 #define C_ES_ATT_LIN_0DB 0x7fff // ref. 0dB |
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618 #define C_ES_ATT_LIN_3DB 0x5A9D // ref. -3dB |
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619 #define C_ES_ATT_LIN_5DB 0x47FA // ref. -5dB |
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620 #define C_ES_ATT_LIN_6DB 0x4026 // ref. -6dB |
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621 #define C_ES_ATT_LIN_8DB 0x32F4 // ref. -8dB |
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622 #define C_ES_ATT_LIN_9DB 0x2D6A // ref. -9dB |
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623 #define C_ES_ATT_LIN_10DB 0x2879 // ref. -10dB |
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624 #define C_ES_ATT_LIN_12DB 0x2026 // ref. -12dB |
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625 #define C_ES_ATT_LIN_15DB 0x16C2 // ref. -15dB |
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626 #define C_ES_ATT_LIN_16DB 0x1449 // ref. -16dB |
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627 #define C_ES_ATT_LIN_19DB 0x0E5D // ref. -19dB |
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628 #define C_ES_ATT_LIN_21DB 0x0B68 // ref. -21dB |
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629 #define C_ES_ATT_LIN_24DB 0x0813 // ref. -24dB |
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630 #define C_ES_ATT_LIN_36DB 0x0207 // ref. -36dB |
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631 #define C_ES_ATT_LIN_48DB 0x0082 // ref. -48dB |
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632 #define C_ES_ATT_LIN_66DB 0x0010 // ref. -56dB |
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633 |
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634 #endif // L1_ES |
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635 #if(L1_EXT_AUDIO_MGT == 1) |
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636 #define AUDIO_EXT_MIDI_BUFFER_SIZE 2640 |
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637 #endif |