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annotate gsm-fw/sysglue/irqfiq.S @ 213:ef7d7da61c56

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FFS code integration: remaining C files imported, but not yet integrated
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 06 Jan 2014 04:20:29 +0000
parents afceeeb2cba1
children
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1 /*
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2 * This module contains the assembly shells for IRQ and FIQ, separated
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3 * from the architectured vectors only by some simple unconditional
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4 * branch instructions.
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5 *
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6 * Note that TI's way of handling interrupts sacrifices Nucleus' ability
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7 * to nest interrupts and minimize the IRQ-disabled window: if my (Falcon's)
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8 * understanding is correct, TI's code leaves all further IRQs disabled
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9 * for the full execution duration of an IRQ handler. (IRQ handlers are
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10 * really LISRs, but TI's GSM fw does not use Nucleus' LISR framework.)
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11 */
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12
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13 .section iram.text,"ax",%progbits
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14 .code 32
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15
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16 .globl _INT_IRQ
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17 _INT_IRQ:
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18 STMDB sp!,{r0-r4} @ used to be a1-a4
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19
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20 /*
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21 * Thanks to TI for discovering and documenting this apparent ARM7TDMI bug:
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22
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23 BUG correction 1st part -------------------
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24 It looks like there is an issue with ARM7 IRQ masking in the CPSR register
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25 which leads to crashes in Nucleus+ scheduler.
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26 Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not
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27 prevent from having an interrupt after the execution of the third line (I mean execution, not
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28 fetch).
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29 MRS a1,CPSR ; Pickup current CPSR
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30 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
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31 MSR CPSR,a1 ; Lockout interrupts
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32 * IRQ INTERRUPT ! *
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33 Next instructions...
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34
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35 SW workaround:
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36 When a task is interrupted at this point an interrupted context is stored on its task and will
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37 be resumed later on at the next instruction but to make a long story short it leads to some
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38 problem as the OS does not expect to be interrupted there.
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39 Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value
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40 but that the IRQ is still triggered (has been hardwarewise requested during the instruction
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41 exectution by the ARM7 core?)
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42 */
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43
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44 MRS a1,spsr @ check for the IRQ bug:
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45 TST a1,#0x80 @ if the I - flag is set,
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46 BNE IRQBUG @ then postpone execution of this IRQ
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47 /* Bug correction 1st part end --------------- */
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48
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49 SUB r4,lr,#4 @ Save IRQ's lr (return address)
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50 BL TCT_Interrupt_Context_Save @ Call context save routine
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51
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52 BL IQ_IRQ_isr @ Call int. service routine
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53
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54 /* IRQ interrupt processing is complete. Restore context- Never
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55 returns! */
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56 B TCT_Interrupt_Context_Restore
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57
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58 /* BUG correction 2nd part ------------------ */
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59 IRQBUG: LDMFD sp!,{r0-r4} @ return from interrupt
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60 SUBS pc,r14,#4
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61 /* BUG correction 2nd part end -------------- */
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62
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63 .globl _INT_FIQ
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64 _INT_FIQ:
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65 STMDB sp!,{r0-r4} @ used to be a1-a4
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66 SUB r4,lr,#4 @ Save FIQ's lr (return address)
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67 BL TCT_Interrupt_Context_Save @ Call context save routine
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68
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69 BL IQ_FIQ_isr @ Call the FIQ ISR
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70
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71 /* FIQ interrupt processing is complete. Restore context- Never
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72 returns! */
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73 B TCT_Interrupt_Context_Restore