FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/abb+spi/abb.h @ 737:f35b7d34153a
rr_datf.c compiles
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 05 Oct 2014 19:03:38 +0000 |
parents | cc0944d35698 |
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rev | line source |
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1 /******************************************************************************/ |
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ |
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3 /* */ |
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */ |
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This*/ |
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6 /* product is protected under copyright law and trade secret law as an*/ |
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All*/ |
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8 /* rights reserved. */ |
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9 /* */ |
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10 /* */ |
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11 /* Filename : abb.h */ |
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12 /* */ |
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13 /* Description : Analog BaseBand registers and bits definition. */ |
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14 /* Functions to drive the ABB device. */ |
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15 /* The Serial Port Interface is used to connect the TI */ |
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16 /* Analog BaseBand (ABB). */ |
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17 /* It is assumed that the ABB is connected as the SPI */ |
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18 /* device 0. */ |
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19 /* */ |
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20 /* Author : Pascal PUEL */ |
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21 /* */ |
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22 /* Version number : 1.3 */ |
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23 /* */ |
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24 /* Date and time : 08/22/03 */ |
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25 /* */ |
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26 /* Previous delta : Creation */ |
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27 /* */ |
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28 /******************************************************************************/ |
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29 |
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30 #ifndef __ABB_H__ |
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31 #define __ABB_H__ |
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32 |
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33 #include "../../include/config.h" |
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34 #include "../../include/sys_types.h" |
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35 |
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36 #ifndef _WINDOWS |
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37 |
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38 /*------------------------------------*/ |
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39 /* SYREN PG Definition */ |
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40 /*------------------------------------*/ |
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41 |
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42 #if (ANALOG == 3) // SYREN |
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43 #define S_PG_10 1 |
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44 #define S_PG_20 2 |
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45 #endif // (ANALOG == 3) |
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46 |
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47 |
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48 |
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49 // DEFINITIONS FOR OMEGA/NAUSICA |
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50 #if (ANALOG == 1) |
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51 // ABB PAGE |
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52 #define PAGE0 0x0001 |
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53 #define PAGE1 0x0002 |
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54 |
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55 // ABB REGISTERS |
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56 //=== PAGE 0 ======= |
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57 #define PAGEREG (1 << 1) |
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58 #define APCDEL1 (2 << 1) |
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59 #define BULDATA1_2 (3 << 1) |
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60 #define TOGBR1 (4 << 1) |
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61 #define TOGBR2 (5 << 1) |
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62 #define VBDCTRL (6 << 1) |
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63 #define AUXAFC1 (7 << 1) |
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64 #define AUXAFC2 (8 << 1) |
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65 #define AUXAPC (9 << 1) |
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66 #define APCRAM (10 << 1) |
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67 #define APCOFF (11 << 1) |
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68 #define AUXDAC (12 << 1) |
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69 #define MADCCTRL1 (13 << 1) |
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70 #define MADCCTRL2 (14 << 1) |
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71 #define VBATREG (15 << 1) |
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72 #define VCHGREG (16 << 1) |
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73 #define ICHGREG (17 << 1) |
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74 #define VBKPREG (18 << 1) |
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75 #define ADIN1REG (19 << 1) |
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76 #define ADIN2REG (20 << 1) |
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77 #define ADIN3REG (21 << 1) |
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78 #define ADIN4XREG (22 << 1) |
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79 #define ADIN5YREG (23 << 1) |
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80 #define MADCSTAT (24 << 1) |
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81 #define CHGREG (25 << 1) |
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82 #define ITMASK (26 << 1) |
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83 #define ITSTATREG (27 << 1) |
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84 #define BCICTL1 (28 << 1) |
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85 #define BCICTL2 (29 << 1) |
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86 #define VRPCCTL2 (30 << 1) |
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87 #define VRPCSTS (31 << 1) |
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88 |
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89 //=== PAGE 1 ======= |
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90 #define PAGEREG (1 << 1) |
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91 #define BULIOFF (2 << 1) |
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92 #define BULQOFF (3 << 1) |
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93 #define BULQDAC (4 << 1) |
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94 #define BULIDAC (5 << 1) |
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95 #define BBCTRL (6 << 1) |
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96 #define VBUCTRL (7 << 1) |
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97 #define VBCTRL (8 << 1) |
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98 #define PWDNRG (9 << 1) |
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99 #define TSC_TIMER (10 << 1) |
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100 #define VRPCCTRL3 (11 << 1) |
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101 #define APCOUT (12 << 1) |
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102 #define VRPCBGT (18 << 1) |
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103 #define TAPCTRL (19 << 1) |
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104 #define TAPREG (20 << 1) |
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105 #define AFCCTLADD (21 << 1) |
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106 #define AFCOUT (22 << 1) |
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107 #define VRPCCTRL1 (23 << 1) |
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108 #define VRPCCTRL4 (24 << 1) |
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109 #define APCDEL2 (26 << 1) |
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110 #define ITSTATREG (27 << 1) |
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111 |
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112 // Registers bit definitions |
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113 // ABB device bits definition of register VBCTRL |
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114 #define VDLAUX 0x001 |
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115 #define VDLEAR 0x002 |
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116 #define VBUZ 0x004 |
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117 #define VULSWITCH 0x008 |
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118 #define MICBIAS 0x010 |
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119 #define VALOOP 0x020 |
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120 #define VCLKMODE 0x040 |
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121 #define VSYNC 0x080 |
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122 #define VBDFAUXG 0x100 |
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123 #define VFBYP 0x200 |
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124 |
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125 // ABB device bits definition of register VBUCTRL |
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126 #define DXEN 0x200 |
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127 |
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128 // ABB device bits definition of register VRPCSTS |
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129 #define ONBSTS 0x01 // ON Button push flag |
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130 #define ONRSTS 0x02 // Remote ON flag |
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131 #define ITWSTS 0x04 // Wake-up IT flag |
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132 #define CHGSTS 0x08 // Charger plug flag |
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133 #define ONREFLT 0x10 // ON Button current state |
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134 #define ORMRFLT 0x20 // Remote ON current state |
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135 #define CHGPRES 0x40 // Charger plug current state |
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136 |
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137 // ABB device bits definition of register ITSTATREG |
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138 #define REMOT_IT_STS 0x02 |
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139 #define PUSHOFF_IT_STS 0x04 |
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140 #define CHARGER_IT_STS 0x08 |
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141 #define ADCEND_IT_STS 0x20 |
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142 |
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143 // On Nausica, if the PWR key is pressed, the bit is set, and cleared when released |
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144 #define PWR_OFF_KEY_PRESSED (ONREFLT) |
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145 |
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146 // ABB ADC Interrupts |
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147 #define EOC_INTENA 0x03DF |
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148 #define EOC_INTMASK 0x0020 |
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149 |
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150 // ABB ADC CHANNELS |
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151 #define VBATCV 0x0001 |
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152 #define VCHGCV 0x0002 |
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153 #define ICHGCV 0x0004 |
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154 #define VBKPCV 0x0008 |
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155 #define ADIN1CV 0x0010 |
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156 #define ADIN2CV 0x0020 |
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157 #define ADIN3CV 0x0040 |
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158 #define vADIN4XCV 0x0080 |
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159 #define ADIN5XCV 0x0100 |
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160 #define ALL 0x01FF |
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161 #define NONE 0x0000 |
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162 |
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163 // ABB MODULES |
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164 #define MADC 0x8000 |
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165 #define AFC 0x2000 |
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166 #define ADAC 0x0800 |
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167 #define DCDC 0x0080 |
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168 #define ALLOFF 0x0000 |
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169 |
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170 // Definitions of OMEGA test modes for baseband windows |
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171 #define TSPTEST1 0x001d |
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172 #define TSPTEST2 0x001e |
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173 #define AFCTEST 0x0010 |
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174 #define AFCNORM 0x0000 |
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175 |
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176 |
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177 // DEFINITIONS FOR IOTA |
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178 #elif (ANALOG == 2) |
148
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179 // ABB PAGE |
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180 #define PAGE0 0x0001 |
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181 #define PAGE1 0x0002 |
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182 #define PAGE2 0x0010 |
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183 |
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184 // ABB REGISTERS |
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185 //=== PAGE 0 ======= |
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186 #define PAGEREG (1 << 1) |
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187 #define APCDEL1 (2 << 1) |
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188 #define BULDATA1_2 (3 << 1) |
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189 #define TOGBR1 (4 << 1) |
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190 #define TOGBR2 (5 << 1) |
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191 #define VBDCTRL (6 << 1) |
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192 #define AUXAFC1 (7 << 1) |
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193 #define AUXAFC2 (8 << 1) |
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194 #define AUXAPC (9 << 1) |
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195 #define APCRAM (10 << 1) |
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196 #define APCOFF (11 << 1) |
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197 #define AUXDAC (12 << 1) |
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198 #define MADCCTRL (13 << 1) |
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199 #define VBATREG (15 << 1) |
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200 #define VCHGREG (16 << 1) |
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201 #define ICHGREG (17 << 1) |
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202 #define VBKPREG (18 << 1) |
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203 #define ADIN1REG (19 << 1) |
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204 #define ADIN2REG (20 << 1) |
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205 #define ADIN3REG (21 << 1) |
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206 #define ADIN4REG (22 << 1) |
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207 #define MADCSTAT (24 << 1) |
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208 #define CHGREG (25 << 1) |
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209 #define ITMASK (26 << 1) |
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210 #define ITSTATREG (27 << 1) |
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211 #define BCICTL1 (28 << 1) |
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212 #define BCICTL2 (29 << 1) |
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213 #define VRPCDEV (30 << 1) |
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214 #define VRPCSTS (31 << 1) |
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215 |
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216 //=== PAGE 1 ======= |
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217 #define PAGEREG (1 << 1) |
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218 #define BULIOFF (2 << 1) |
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219 #define BULQOFF (3 << 1) |
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220 #define BULQDAC (4 << 1) |
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221 #define BULIDAC (5 << 1) |
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222 #define BBCTRL (6 << 1) |
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223 #define VBUCTRL (7 << 1) |
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224 #define VBCTRL1 (8 << 1) |
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225 #define PWDNRG (9 << 1) |
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226 #define VBPOP (10 << 1) |
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227 #define VBCTRL2 (11 << 1) |
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228 #define APCOUT (12 << 1) |
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229 #define BCICONF (13 << 1) |
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230 #define BULGCAL (14 << 1) |
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231 #define TAPCTRL (19 << 1) |
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232 #define TAPREG (20 << 1) |
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233 #define AFCCTLADD (21 << 1) |
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234 #define AFCOUT (22 << 1) |
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235 #define VRPCSIM (23 << 1) |
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236 #define AUXLED (24 << 1) |
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237 #define APCDEL2 (26 << 1) |
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238 #define ITSTATREG (27 << 1) |
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239 #define VRPCMSKABB (29 << 1) |
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240 #define VRPCCFG (30 << 1) |
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241 #define VRPCMSK (31 << 1) |
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242 |
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243 // Registers bit definitions |
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244 // ABB device bits definition of register VBCTRL1 |
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245 #define VDLAUX 0x001 |
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246 #define VDLEAR 0x002 |
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247 #define VBUZ 0x004 |
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248 #define VULSWITCH 0x008 |
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249 #define MICBIAS 0x010 |
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250 #define VALOOP 0x020 |
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251 #define VCLKMODE 0x040 |
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252 #define VSYNC 0x080 |
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253 #define VBDFAUXG 0x100 |
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254 #define VFBYP 0x200 |
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255 |
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256 // ABB device bits definition of register VBCTRL2 |
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257 #define MICBIASEL 0x001 |
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258 #define VDLHSO 0x002 |
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259 #define MICNAUX 0x004 |
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260 |
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261 // ABB device bits definition of register VBUCTRL |
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262 #define DXEN 0x200 |
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263 |
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264 // ABB device bits definition of register VBPOP |
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265 #define HSODIS 0x001 |
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266 #define HSOCHG 0x002 |
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267 #define HSOAUTO 0x004 |
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268 #define EARDIS 0x008 |
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269 #define EARCHG 0x010 |
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270 #define EARAUTO 0x020 |
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271 #define AUXDIS 0x040 |
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272 #define AUXCHG 0x080 |
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273 #define AUXAUTO 0x100 |
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274 |
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275 // ABB device bits definition of register VRPCSTS |
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276 #define ONBSTS 0x01 // ON Button push flag |
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277 #define ONRSTS 0x02 // Remote ON flag |
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278 #define ITWSTS 0x04 // Wake-up IT flag |
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279 #define CHGSTS 0x08 // Charger plug flag |
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280 #define ONREFLT 0x10 // ON Button current state |
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281 #define ORMRFLT 0x20 // Remote ON current state |
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282 #define CHGPRES 0x40 // Charger plug current state |
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283 |
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284 // ABB device bits definition of register ITSTATREG |
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285 #define REMOT_IT_STS 0x02 |
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286 #define PUSHOFF_IT_STS 0x04 |
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287 #define CHARGER_IT_STS 0x08 |
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288 #define ADCEND_IT_STS 0x20 |
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289 |
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290 // On Iota, the bit is set when the key is released and set when the key is pressed |
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291 #define PWR_OFF_KEY_PRESSED (0) |
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292 |
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293 // ABB ADC Interrupts |
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294 #define EOC_INTENA 0x03DF |
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295 #define EOC_INTMASK 0x0020 |
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296 |
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297 // ABB ADC CHANNELS |
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298 #define VBATCV 0x0001 |
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299 #define VCHGCV 0x0002 |
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300 #define ICHGCV 0x0004 |
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301 #define VBKPCV 0x0008 |
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302 #define ADIN1CV 0x0010 |
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303 #define ADIN2CV 0x0020 |
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304 #define ADIN3CV 0x0040 |
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305 #define ADIN4CV 0x0080 |
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306 #define ALL 0x00FF |
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307 #define NONE 0x0000 |
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308 |
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309 // ABB MODULES |
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310 #define MADC 0x8000 |
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311 #define AFC 0x2000 |
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312 #define ADAC 0x0800 |
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313 #define DCDC 0x0080 |
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314 #define ALLOFF 0x0000 |
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315 |
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316 // Definitions of IOTA test modes |
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317 #define TSPTEST1 0x001d |
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318 #define TSPTEST2 0x001e |
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319 #define AFCTEST 0x0010 |
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320 #define AFCNORM 0x0000 |
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321 |
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322 // Definition for IOTA test modes |
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323 #define TSPEN 0x001a |
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324 #define MADCTEST 0x0012 |
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325 #define TSPADC 0x0015 |
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326 #define TSPUP 0x0017 |
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327 #define TSPDN 0x0018 |
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328 |
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329 // Definition for IOTA Power Management |
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330 |
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331 //The duration of the SLPDLY counter must be greater than the process execution time: |
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332 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check |
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333 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay |
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334 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and |
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335 // write DEVSLEEP = 0 |
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336 |
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337 |
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338 |
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339 |
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340 #define SLPDLY 0x001F // delay to set IOTA in sleep mode (unit: 20*T32Khz) |
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341 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode |
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342 |
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343 |
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344 // DEFINITIONS FOR SYREN |
149
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345 #elif (ANALOG == 3) |
148
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346 |
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347 // ABB PAGE |
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348 #define PAGE0 0x0001 |
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349 #define PAGE1 0x0002 |
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350 #define PAGE2 0x0010 |
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351 |
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352 // ABB REGISTERS |
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353 //=== PAGE 0 ======= |
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354 #define PAGEREG (1 << 1) |
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355 #define APCDEL1 (2 << 1) |
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356 #define BULDATA1_2 (3 << 1) |
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357 #define TOGBR1 (4 << 1) |
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358 #define TOGBR2 (5 << 1) |
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359 #define VBDCTRL (6 << 1) |
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360 #define AUXAFC1 (7 << 1) |
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361 #define AUXAFC2 (8 << 1) |
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362 #define AUXAPC (9 << 1) |
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363 #define APCRAM (10 << 1) |
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364 #define APCOFF (11 << 1) |
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365 #define AUXDAC (12 << 1) |
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366 #define MADCCTRL (13 << 1) |
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367 #define CHGIREG (14 << 1) |
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368 #define VBATREG (15 << 1) |
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369 #define VCHGREG (16 << 1) |
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370 #define ICHGREG (17 << 1) |
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371 #define VBKPREG (18 << 1) |
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372 #define ADIN1REG (19 << 1) |
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373 #define ADIN2REG (20 << 1) |
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374 #define ADIN3REG (21 << 1) |
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375 #define ADIN4REG (22 << 1) |
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376 #define ADIN5REG (23 << 1) |
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377 #define MADCSTAT (24 << 1) |
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378 #define CHGVREG (25 << 1) |
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379 #define ITMASK (26 << 1) |
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380 #define ITSTATREG (27 << 1) |
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381 #define BCICTL1 (28 << 1) |
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382 #define BCICTL2 (29 << 1) |
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383 #define VRPCDEV (30 << 1) |
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384 #define VRPCSTS (31 << 1) |
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385 |
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386 //=== PAGE 1 ======= |
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387 #define PAGEREG (1 << 1) |
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388 #define BULIOFF (2 << 1) |
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389 #define BULQOFF (3 << 1) |
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390 #define BULQDAC (4 << 1) |
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391 #define BULIDAC (5 << 1) |
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392 #define BBCTRL (6 << 1) |
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393 #define VBUCTRL (7 << 1) |
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394 #define VBCTRL1 (8 << 1) |
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395 #define PWDNRG (9 << 1) |
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396 #define VBPOP (10 << 1) |
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397 #define VBCTRL2 (11 << 1) |
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398 #define APCOUT (12 << 1) |
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399 #define BCICONF (13 << 1) |
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400 #define BULGCAL (14 << 1) |
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401 #define VAUDCTRL (15 << 1) |
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402 #define VAUSCTRL (16 << 1) |
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403 #define VAUOCTRL (17 << 1) |
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404 #define VAUDPLL (18 << 1) |
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405 #define TAPCTRL (19 << 1) |
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406 #define TAPREG (20 << 1) |
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407 #define AFCCTLADD (21 << 1) |
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408 #define AFCOUT (22 << 1) |
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409 #define VRPCSIMR (23 << 1) |
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410 #define BCIWDOG (24 << 1) |
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411 #define NONE8 (25 << 1) |
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412 #define APCDEL2 (26 << 1) |
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413 #define ITSTATREG (27 << 1) |
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414 |
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415 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO |
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416 #define BBCFG (28 << 1) |
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417 #else |
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418 #define NONE9 (28 << 1) |
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419 #endif |
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420 |
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421 #define VRPCMSKOFF (29 << 1) |
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422 #define VRPCCFG (30 << 1) |
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423 #define VRPCMSKSLP (31 << 1) |
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424 |
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425 //=== PAGE 2 ======= |
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426 |
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427 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
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428 #define BBCFG (5 << 1) |
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429 #endif |
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430 |
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431 #define VRPCABBTST (25 << 1) |
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432 #define VRPCAUX (30 << 1) |
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433 #define VRPCLDO (31 << 1) |
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434 |
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435 /* INSERT HERE OTHER DEVICES REGISTERS */ |
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436 |
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437 |
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438 // Registers bit definitions |
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439 /*** SYREN internal control bits ***/ |
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440 |
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441 /** For reg. VBCTRL1 **/ |
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442 #define VULSWITCH 0x008 |
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443 #define MICBIAS 0x010 |
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444 #define VALOOP 0x020 |
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445 #define VCLKMODE 0x040 |
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446 #define VSYNC 0x080 |
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447 #define VBDFAUXG 0x100 |
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448 #define VFBYP 0x200 |
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449 |
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450 /** For reg. VBCTRL2 **/ |
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451 #define HSMICSEL 0x001 |
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452 #define MICBIASEL 0x004 |
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453 #define SPKG 0x008 |
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454 #define HSOVMID 0x010 |
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455 #define HSDIF 0x020 |
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456 |
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457 /** For reg. VBUCTRL **/ |
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458 #define DXEN 0x200 |
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459 |
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460 /** For reg. VBPOP **/ |
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461 #define HSODIS 0x001 |
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462 #define HSOCHG 0x002 |
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463 #define HSOAUTO 0x004 |
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464 #define EARDIS 0x008 |
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465 #define EARCHG 0x010 |
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466 #define EARAUTO 0x020 |
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467 #define AUXFDIS 0x040 |
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468 #define AUXAUTO 0x080 |
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469 #define AUXFBYP 0x200 |
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470 |
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471 // ABB device bits definition of register VRPCCFG |
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472 #define PWOND 0x20 // ON Button current state |
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473 #define CHGPRES 0x40 |
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474 |
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475 // ABB device bits definition of register ITSTATREG |
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476 #define REMOT_IT_STS 0x02 |
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477 #define PUSHOFF_IT_STS 0x04 |
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478 #define CHARGER_IT_STS 0x08 |
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479 #define ADCEND_IT_STS 0x20 |
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480 |
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481 // ABB device bits definition of register VRPCSTS |
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482 #define ITWSTS 0x10 // Wake-up IT flag |
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483 #define PWONBSTS 0x20 // ON Button push flag |
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484 #define CHGSTS 0x40 // Charger plug flag |
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485 #define RPSTS 0x100 // Remote ON flag |
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486 |
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487 // ABB ADC Interrupts |
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488 #define EOC_INTENA 0x03DF |
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489 #define EOC_INTMASK 0x0020 |
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490 |
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491 // ABB ADC CHANNELS (reg. MADCCTRL) |
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492 #define VBATCV 0x0001 |
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493 #define VCHGCV 0x0002 |
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494 #define ICHGCV 0x0004 |
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495 #define VBKPCV 0x0008 |
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496 #define ADIN1CV 0x0010 |
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497 #define ADIN2CV 0x0020 |
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498 #define ADIN3CV 0x0040 |
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499 #define ADIN4CV 0x0080 |
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500 #define ADIN5CV 0x0100 |
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501 #define ALL 0x01FF |
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502 #define NONE 0x0000 |
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503 |
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504 // ABB MODULES |
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505 #define MADC 0x8000 |
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506 #define AFC 0x2000 |
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507 #define ADAC 0x0800 |
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508 #define DCDC 0x0080 |
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509 #define ALLOFF 0x0000 |
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510 |
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511 // Definitions of SYREN test modes |
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512 #define TSPTEST1 0x001d |
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513 #define TSPTEST2 0x001e |
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514 #define AFCTEST 0x0010 |
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515 #define AFCNORM 0x0000 |
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516 |
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517 #define TSPEN 0x001a |
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518 #define MADCTEST 0x0012 |
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519 #define TSPADC 0x0015 |
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520 #define TSPUP 0x0017 |
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521 #define TSPDN 0x0018 |
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522 |
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523 // Definition for SYREN Power Management |
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524 |
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525 //The duration of the SLPDLY counter must be greater than the process execution time: |
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526 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check |
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527 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay |
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528 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and |
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529 // write DEVSLEEP = 0 |
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530 |
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531 #define SLPDLY 0x001F // delay to set SYREN in sleep mode (unit: 20*T32Khz) |
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532 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode |
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533 |
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534 #define LOCORE_SLEEP 0x01 |
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535 #define NORMAL_SLEEP 0x00 |
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536 |
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537 #define MAIN_BG 0x01, |
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538 #define SLEEP_BG 0x00 |
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539 |
149
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540 #endif // ANALOG == 1,2,3 |
148
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541 |
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542 |
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543 // Define the level of semaphore protection for all accesses to the ABB |
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544 // 0 for no protection |
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545 // 1 for protection low |
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546 // 2 for protection medium |
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547 // 3 for protection high |
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548 #if (OP_L1_STANDALONE == 1) |
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549 #define ABB_SEMAPHORE_PROTECTION (0) |
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550 #else |
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551 #define ABB_SEMAPHORE_PROTECTION (1) |
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552 #endif |
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553 |
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554 |
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555 |
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556 // PROTOTYPES |
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557 #if (ABB_SEMAPHORE_PROTECTION) |
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558 void ABB_Sem_Create(void); |
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559 #endif |
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560 void ABB_Wait_IBIC_Access(void); |
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561 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value); |
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562 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id); |
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563 void ABB_free_13M(void); |
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564 void ABB_stop_13M(void); |
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565 SYS_UWORD16 ABB_Read_Status(void); |
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566 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal); |
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567 void ABB_Read_ADC(SYS_UWORD16 *Buff); |
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568 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag); |
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569 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc); |
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570 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc); |
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571 void ABB_wa_VRPC(SYS_UWORD16 value); |
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572 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data); |
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573 #if (OP_L1_STANDALONE == 0) |
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574 void ABB_Power_Off(void); |
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575 #endif |
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576 #if (ANALOG ==3) |
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577 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay); |
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578 #endif |
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579 |
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580 #else // _WINDOWS |
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581 // DEFINITIONS FOR IOTA |
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582 // ABB PAGE |
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583 #define PAGE0 0x0001 |
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584 #define PAGE1 0x0002 |
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585 #define PAGE2 0x0010 |
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586 |
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587 // ABB REGISTERS |
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588 //=== PAGE 0 ======= |
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589 #define PAGEREG (1 << 1) |
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590 #define APCDEL1 (2 << 1) |
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591 #define BULDATA1_2 (3 << 1) |
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592 #define TOGBR1 (4 << 1) |
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593 #define TOGBR2 (5 << 1) |
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594 #define VBDCTRL (6 << 1) |
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595 #define AUXAFC1 (7 << 1) |
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596 #define AUXAFC2 (8 << 1) |
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597 #define AUXAPC (9 << 1) |
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598 #define APCRAM (10 << 1) |
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599 #define APCOFF (11 << 1) |
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600 #define AUXDAC (12 << 1) |
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601 #define MADCCTRL (13 << 1) |
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602 #define VBATREG (15 << 1) |
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603 #define VCHGREG (16 << 1) |
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604 #define ICHGREG (17 << 1) |
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605 #define VBKPREG (18 << 1) |
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606 #define ADIN1REG (19 << 1) |
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607 #define ADIN2REG (20 << 1) |
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608 #define ADIN3REG (21 << 1) |
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609 #define ADIN4REG (22 << 1) |
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610 #define MADCSTAT (24 << 1) |
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611 #define CHGREG (25 << 1) |
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612 #define ITMASK (26 << 1) |
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613 #define ITSTATREG (27 << 1) |
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614 #define BCICTL1 (28 << 1) |
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615 #define BCICTL2 (29 << 1) |
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616 #define VRPCDEV (30 << 1) |
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617 #define VRPCSTS (31 << 1) |
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618 |
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619 //=== PAGE 1 ======= |
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620 #define PAGEREG (1 << 1) |
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621 #define BULIOFF (2 << 1) |
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622 #define BULQOFF (3 << 1) |
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623 #define BULQDAC (4 << 1) |
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624 #define BULIDAC (5 << 1) |
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625 #define BBCTRL (6 << 1) |
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626 #define VBUCTRL (7 << 1) |
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627 #define VBCTRL1 (8 << 1) |
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628 #define PWDNRG (9 << 1) |
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629 #define VBPOP (10 << 1) |
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630 #define VBCTRL2 (11 << 1) |
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631 #define APCOUT (12 << 1) |
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632 #define BCICONF (13 << 1) |
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633 #define BULGCAL (14 << 1) |
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634 #define TAPCTRL (19 << 1) |
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635 #define TAPREG (20 << 1) |
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636 #define AFCCTLADD (21 << 1) |
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637 #define AFCOUT (22 << 1) |
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638 #define VRPCSIM (23 << 1) |
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639 #define AUXLED (24 << 1) |
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640 #define APCDEL2 (26 << 1) |
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641 #define ITSTATREG (27 << 1) |
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642 #define VRPCMSKABB (29 << 1) |
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643 #define VRPCCFG (30 << 1) |
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644 #define VRPCMSK (31 << 1) |
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645 |
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646 // ABB device bits definition of register VBUCTRL |
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647 #define DXEN 0x200 |
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648 |
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649 // ABB device bits definition of register VRPCSTS |
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650 #define ONBSTS 0x01 // ON Button push flag |
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651 #define ONRSTS 0x02 // Remote ON flag |
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652 #define ITWSTS 0x04 // Wake-up IT flag |
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653 #define CHGSTS 0x08 // Charger plug flag |
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654 #define ONREFLT 0x10 // ON Button current state |
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655 #define ORMRFLT 0x20 // Remote ON current state |
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656 #define CHGPRES 0x40 // Charger plug current state |
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657 |
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658 // ABB device bits definition of register ITSTATREG |
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659 #define REMOT_IT_STS 0x02 |
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660 #define PUSHOFF_IT_STS 0x04 |
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661 #define CHARGER_IT_STS 0x08 |
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662 #define ADCEND_IT_STS 0x20 |
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663 |
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664 |
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665 // PROTOTYPES |
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666 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD32 value); |
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667 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id); |
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668 SYS_UWORD16 ABB_Read_Status(void); |
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669 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal); |
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670 void ABB_Read_ADC(SYS_UWORD16 *Buff); |
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671 |
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672 #endif // _WINDOWS |
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673 |
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674 #endif // __ABB_H__ |