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annotate nuc-fw/finlink/ld-script.src @ 92:f459043fae0c

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nuc-fw config: ld script generation implemented
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 25 Aug 2013 21:20:20 +0000
parents
children 2c5160a9d652
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92
f459043fae0c nuc-fw config: ld script generation implemented
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1 dnl This ld script source is fed through m4 in order to fill in
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2 dnl those settings which depend on the configuration.
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3 dnl Memory region sizes are set in ../include/config.m4, generated
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4 dnl by the configuration mechanism based on the selected target,
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5 dnl and the Makefile prepends flash.m4 or xram.m4 to select the
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6 dnl type of image we are linking: either the regular flashable image,
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7 dnl or a RAM-only test image (to be loaded via fc-xram) that does not
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8 dnl touch the flash and pretends as if the flash doesn't even exist.
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9
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10 /*
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11 * FreeCalypso ld script for the Buildmem build
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12 */
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13
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14 ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,0))
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15
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16 include(`../include/config.m4')dnl
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17 MEMORY {
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18 ifelse(Buildmem,FLASH,
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19 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000
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20 FLASH : ORIGIN = 0x2000, LENGTH = CONFIG_FWFLASH_SIZE - 0x2000')
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21 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
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22 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
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23 }
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24
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25 SECTIONS {
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26 /* XIP code, going into flash or XRAM emulating flash */
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27 xip.text : {
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28 *(xip.text*)
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29 xipcode.o(.text*)
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30 *libplus.xip.a:(.text*)
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31 *libsprintf.a:(.text*)
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32 /* let's put the ARM->Thumb veneers in the XIP section */
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33 *(.glue_7)
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34 } > Buildmem
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35
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36 /* copy-to-IRAM code */
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37 iram.text 0x80001C : {
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38 /* the 7 exception and interrupt vectors @ 0x80001C */
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39 *(iram.vectors)
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40 *(iram.text*)
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41 iramcode.o(.text*)
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42 *libplus.iram.a:(.text*)
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43 *libc.a:(.text*)
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44 *libgcc.a:(.text*)
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45 } > IRAM AT> Buildmem
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46 __iramtext_ram_addr = ADDR(iram.text);
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47 __iramtext_flash_addr = LOADADDR(iram.text);
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48 __iramtext_size = SIZEOF(iram.text);
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49
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50 /* all .rodata will stay in flash */
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51 .rodata : {
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52 *(.rodata*)
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53 } > Buildmem
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54
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55 /*
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56 * All .data will go into XRAM.
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57 * For the flash build we'll have a step that copies
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58 * the .data section from flash to XRAM; for the RAM-only
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59 * build it goes directly into XRAM and stays there.
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60 */
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61 .data : {
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62 *(.data*)
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63 } > XRAM AT> Buildmem
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64 ifelse(Buildmem,FLASH,
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65 ` __initdata_ram_addr = ADDR(.data);
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66 __initdata_flash_addr = LOADADDR(.data);
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67 __initdata_size = SIZEOF(.data);
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68 ')dnl
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69
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70 /* we have two kinds of BSS: internal and external */
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71 int.bss (NOLOAD) : {
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72 *(int.bss*)
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73 iramcode.o(.bss* COMMON)
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74 *libplus.iram.a:(.bss* COMMON)
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75 *libc.a:(.bss* COMMON)
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76 *libgcc.a:(.bss* COMMON)
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77 . = ALIGN(4);
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78 } > IRAM
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79 __intbss_start = ADDR(int.bss);
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80 __intbss_size = SIZEOF(int.bss);
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81
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82 ext.bss (NOLOAD) : {
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83 *(ext.bss*)
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84 xipcode.o(.bss* COMMON)
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85 *libplus.xip.a:(.bss* COMMON)
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86 *libsprintf.a:(.bss* COMMON)
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87 . = ALIGN(4);
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88 } > XRAM
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89 __extbss_start = ADDR(ext.bss);
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90 __extbss_size = SIZEOF(ext.bss);
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91
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92 /* finally, we have "raw RAM": like BSS, but we don't zero it out */
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93 int.ram (NOLOAD) : {
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94 *(int.ram*)
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95 *(system_stack)
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96 *(irq_stack)
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97 *(fiq_stack)
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98 *(timer_hisr_stack)
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99 . = ALIGN(4);
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100 _iram_end = .;
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101 } > IRAM
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102
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103 ext.ram (NOLOAD) : {
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104 *(ext.ram*)
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105 . = ALIGN(4);
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106 _xram_end = .;
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107 } > XRAM
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108 }