FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/finlink/ld-script.src @ 912:f50c71442d50

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etmsync: die ID read implemented
author Space Falcon <falcon@ivan.Harhan.ORG>
date Tue, 08 Sep 2015 08:18:42 +0000
parents ab20a5e9dbf3
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 dnl This ld script source is fed through m4 in order to fill in
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2 dnl those settings which depend on the configuration.
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3 dnl Memory region sizes are set in ../include/config.m4, generated
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4 dnl by the configuration mechanism based on the selected target,
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5 dnl and the Makefile prepends flash.m4 or xram.m4 to select the
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6 dnl type of image we are linking: either the regular flashable image,
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7 dnl or a RAM-only test image (to be loaded via fc-xram) that does not
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8 dnl touch the flash and pretends as if the flash doesn't even exist.
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9
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10 /*
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11 * FreeCalypso ld script for the Buildmem build
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12 */
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13
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14 ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,_Flash_boot_entry))
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15
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16 include(`../include/config.m4')dnl
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17 MEMORY {
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18 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
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19 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000')
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20 ifelse(Buildmem,FLASH,
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21 ` FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR,
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22 LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR')
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23 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
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24 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
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25 }
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26 ifelse(FFS_IN_RAM,1,`
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27 RAMFFS_BLKSIZE_BYTES = 1 << RAMFFS_BLKSIZE_LOG2;
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28 RAMFFS_TOTAL_SIZE = RAMFFS_BLKSIZE_BYTES * RAMFFS_NBLOCKS;
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29 ')dnl
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30
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31 SECTIONS {
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32 dnl The following sections exist only in the flashImage build,
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33 dnl and only on targets that use the Calypso boot ROM.
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34 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
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35 ` /* Part of flash overlaid by the boot ROM */
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36 bootrom.overlay 0 : {
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37 *(bootrom.overlay)
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38 } > FLASH_OVERLAY
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39
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40 /* code that enables the boot ROM and jumps to it */
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41 bootrom.switch : {
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42 *(bootrom.switch)
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43 } > IRAM AT> FLASH_OVERLAY
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44 __romswitch_ram_addr = ADDR(bootrom.switch);
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45 __romswitch_flash_addr = LOADADDR(bootrom.switch);
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46 __romswitch_size = SIZEOF(bootrom.switch);
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47 ')dnl
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48
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49 dnl all flashImage builds
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50 ifelse(Buildmem,FLASH,
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51 ` /* Flash boot entry point */
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52 flashboot.text FLASHIMAGE_BASE_ADDR : {
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53 *(flashboot.text)
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54 } > FLASH
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55 ')dnl
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56
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57 /* XIP code, going into flash or XRAM emulating flash */
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58 xip.text : {
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59 *(xip.text*)
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60 xipcode.o(.text*)
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61 *comlib.a:(.text*)
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62 *libdsp.a:(.text*)
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63 *libdti.a:(.text*)
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64 *libgdi.a:(.text*)
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65 *libplus.xip.a:(.text*)
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66 *libgpf.xip.a:(.text*)
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67 *libccd.a:(.text*)
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68 *librv.a:(.text*)
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69 *libsprintf.a:(.text*)
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70 /* let's put the ARM->Thumb veneers in the XIP section */
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71 *(.glue_7)
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72 } > Buildmem
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73
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74 /* copy-to-IRAM code */
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75 iram.text 0x80001C : {
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76 /* the 7 exception and interrupt vectors @ 0x80001C */
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77 *(iram.vectors)
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78 *(iram.text*)
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79 iramcode.o(.text*)
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80 *libplus.iram.a:(.text*)
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81 *libgpf.iram.a:(.text*)
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82 *libiram.a:(.text*)
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83 *libc.a:(.text*)
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84 *libgcc.a:(.text*)
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85 } > IRAM Put_in_flash
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86 ifelse(Buildmem,FLASH,
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87 ` __iramtext_ram_addr = ADDR(iram.text);
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88 __iramtext_flash_addr = LOADADDR(iram.text);
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89 __iramtext_size = SIZEOF(iram.text);
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90 ')dnl
92
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91
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92 /* all .rodata will stay in flash */
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93 .rodata : {
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94 *(.rodata*)
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95 } > Buildmem
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96
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97 /*
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98 * All .data will go into XRAM.
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99 * For the flash build we'll have a step that copies
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100 * the .data section from flash to XRAM; for the RAM-only
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101 * build it goes directly into XRAM and stays there.
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102 */
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103 .data : {
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104 *(.data*)
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105 } > XRAM Put_in_flash
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106 ifelse(Buildmem,FLASH,
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107 ` __initdata_ram_addr = ADDR(.data);
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108 __initdata_flash_addr = LOADADDR(.data);
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109 __initdata_size = SIZEOF(.data);
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110 ')dnl
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111
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112 /* we have two kinds of BSS: internal and external */
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113 int.bss (NOLOAD) : {
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114 *(int.bss*)
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115 *(.l1s_global)
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116 iramcode.o(.bss* COMMON)
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117 *libplus.iram.a:(.bss* COMMON)
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118 *libgpf.iram.a:(.bss* COMMON)
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119 *libiram.a:(.bss* COMMON)
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120 *libc.a:(.bss* COMMON)
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121 *libgcc.a:(.bss* COMMON)
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122 . = ALIGN(4);
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123 } > IRAM
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124 __intbss_start = ADDR(int.bss);
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125 __intbss_size = SIZEOF(int.bss);
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126
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127 ext.bss (NOLOAD) : {
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128 *(ext.bss*)
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129 xipcode.o(.bss* COMMON)
671
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parents: 658
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130 *comlib.a:(.bss* COMMON)
899
ab20a5e9dbf3 gsm-fw/L1/dsp code made into a library in preparation for adding patch codes
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parents: 860
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131 *libdsp.a:(.bss* COMMON)
849
6620bb8e3fa5 gsm-fw/finlink/ld-script.src: take care of bss from libdti and libgdi
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parents: 843
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132 *libdti.a:(.bss* COMMON)
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parents: 843
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133 *libgdi.a:(.bss* COMMON)
92
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134 *libplus.xip.a:(.bss* COMMON)
489
2a26785fb5a2 gsm-fw: GPF included in the build with feature gpf, link successful
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parents: 312
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135 *libgpf.xip.a:(.bss* COMMON)
658
46e5c90fd0b8 gsm-fw: ccd hooked into the build
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 636
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136 *libccd.a:(.bss* COMMON)
132
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 92
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137 *librv.a:(.bss* COMMON)
92
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138 *libsprintf.a:(.bss* COMMON)
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139 . = ALIGN(4);
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140 } > XRAM
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141 __extbss_start = ADDR(ext.bss);
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142 __extbss_size = SIZEOF(ext.bss);
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143
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144 /* finally, we have "raw RAM": like BSS, but we don't zero it out */
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145 int.ram (NOLOAD) : {
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146 *(int.ram*)
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147 *(system_stack)
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148 *(irq_stack)
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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149 *(fiq_stack)
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150 *(timer_hisr_stack)
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151 . = ALIGN(4);
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152 _iram_end = .;
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153 } > IRAM
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154
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155 ext.ram (NOLOAD) : {
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156 *(ext.ram*)
312
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parents: 208
diff changeset
157 *(except_stack)
92
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158 . = ALIGN(4);
208
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 143
diff changeset
159 ifelse(FFS_IN_RAM,1,
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parents: 143
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160 ` _RAMFFS_area = .;
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parents: 143
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161 . += RAMFFS_TOTAL_SIZE;
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parents: 143
diff changeset
162 ')dnl
92
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163 _xram_end = .;
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164 } > XRAM
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165 }