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annotate gsm-fw/services/ffs/intelsbdrv.c @ 1020:fab048ff04b8

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doc/Freerunner-Howto: update for voice calls working with the FR codec
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 23 Apr 2016 05:17:15 +0000
parents 51f580665110
children
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1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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1 /******************************************************************************
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2 * Flash File System (ffs)
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
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4 *
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5 * FFS AMD single bank low level flash driver RAM code
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6 *
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
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8 *
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9 ******************************************************************************/
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10
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11 #include "../../include/config.h"
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12 #include "ffs.h"
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13 #include "drv.h"
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14 #include "ffstrace.h"
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15 #include "intctl.h"
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16
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17 #define INTEL_UNLOCK_SLOW 1
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19 #undef tlw
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20 #define tlw(contents)
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21 #undef ttw
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22 #define ttw(contents)
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1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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24 // Status bits for Intel flash memory devices
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25 #define INTEL_STATE_MACHINE_DONE (1<<7)
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26 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
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27 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
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29 /******************************************************************************
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30 * INTEL Single Bank Driver Functions
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31 ******************************************************************************/
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32 // Actually we should have disabled and enable the interrupts in this
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33 // function, but when the interrupt functions are used Target don't run!
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34 // Anyway, currently the interrupts are already disabled at this point thus
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35 // it does not cause any problems.
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36 int ffsdrv_ram_intel_sb_init(void)
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37 {
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38 uint32 i;
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39 volatile uint16 *addr;
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1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
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41 for (i = 0; i < dev.numblocks; i++)
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42 {
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43 addr = (volatile uint16 *) block2addr(i);
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45 *addr = 0x60; // Intel Config Setup
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46 *addr = 0xD0; // Intel Unlock Block
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47
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48 *addr = 0xFF; // Intel Read Array
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49 }
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51 return 0;
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52 }
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54 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
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55 {
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56 uint32 cpsr;
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57
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58 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
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59
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60 if (~*addr & value) {
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61 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
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62 return;
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63 }
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64
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65 cpsr = int_disable();
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66 tlw(led_on(LED_WRITE));
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67
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68 #if (INTEL_UNLOCK_SLOW == 1)
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69 *addr = 0x60; // Intel Config Setup
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70 *addr = 0xD0; // Intel Unlock Block
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71 #endif
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72
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73 *addr = 0x50; // Intel Clear Status Register
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74 *addr = 0x40; // Intel program byte/word
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75 *addr = value;
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76 while ((*addr & 0x80) == 0)
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77 ;
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78 *addr = 0xFF; // Intel read array
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79 tlw(led_off(LED_WRITE));
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80 int_enable(cpsr);
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81 }
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82
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83 void ffsdrv_ram_intel_sb_erase(uint8 block)
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84 {
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85 volatile uint16 *addr;
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86 uint32 cpsr;
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87 uint16 poll;
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88
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89 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
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90
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91 addr = (volatile uint16 *) block2addr(block);
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92
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93 cpsr = int_disable();
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94 tlw(led_on(LED_ERASE));
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95
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96 #if (INTEL_UNLOCK_SLOW == 1)
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97 *addr = 0x60; // Intel Config Setup
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98 *addr = 0xD0; // Intel Unlock Block
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99 #endif
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100
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101 *addr = 0x50; // Intel Clear Status Register
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102 *addr = 0x20; // Intel Erase Setup
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103 *addr = 0xD0; // Intel Erase Confirm
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104 *addr = 0x70; // Intel Read Status Register
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105
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106 // Wait for erase to finish.
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107 while ((*addr & 0x80) == 0) {
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108 tlw(led_toggle(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
109 // Poll interrupts, taking interrupt mask into account.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
110 if (INT_REQUESTED)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
111 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
112 // 1. suspend erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
113 // 2. enable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
114 // .. now the interrupt code executes
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
115 // 3. disable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
116 // 4. resume erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
117
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
118 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
119
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
120 *addr = 0xB0; // Intel Erase Suspend
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
121 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
122 while (((poll = *addr) & 0x80) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
123 ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
124
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
125 // If erase is complete, exit immediately
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
126 if ((poll & 0x40) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
127 break;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
128
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
129 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
130
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
131 tlw(led_off(LED_ERASE_SUSPEND));
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
132 int_enable(cpsr);
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
133
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
134 // Other interrupts and tasks run now...
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
135
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
136 cpsr = int_disable();
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
137 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
138
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
139 *addr = 0xD0; // Intel erase resume
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
140 // The following "extra" Read Status command is required because Intel has
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
141 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
142 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
143 // Specification Update")
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
144 *addr = 0x70; // Intel Read Status Register
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
145
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
146 tlw(led_off(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
147 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
148 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
149 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
150
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
151 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
152 tlw(led_off(LED_ERASE));
939
62ca61292b77 gsm-fw: Intel single bank flash driver (Compal) compiles and links
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents: 938
diff changeset
153 int_enable(cpsr);
938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
154 }