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annotate target-utils/pirexplore/lcd.c @ 77:fcbe1332b197

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pirexplore: LCD init and BL control work now
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Thu, 01 Aug 2013 00:57:49 +0000
parents 07b686248ab7
children 2c266d4339ff
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1 #include <sys/types.h>
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2 #include "types.h"
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3
76
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4 #define GPIO_OUT_REG (*(volatile u16 *)0xFFFE4802)
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5 #define nCS4_ADDR0 (*(volatile u16 *)0x02800000)
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6 #define nCS4_ADDR2 (*(volatile u16 *)0x02800002)
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7
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8 fb_spca_write(addr, data)
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9 {
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10 GPIO_OUT_REG &= 0xFF7F;
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11 nCS4_ADDR0 = addr;
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12 nCS4_ADDR2 = data;
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13 }
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14
74
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15 void
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16 cmd_spca(argbulk)
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17 char *argbulk;
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18 {
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19 char *argv[3];
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20 u_long addr, data;
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21
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22 if (parse_args(argbulk, 2, 2, argv, 0) < 0)
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23 return;
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24 if (parse_hexarg(argv[0], 4, &addr) < 0) {
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25 printf("ERROR: arg1 must be a valid 16-bit hex value\n");
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26 return;
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27 }
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28 if (parse_hexarg(argv[1], 4, &data) < 0) {
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29 printf("ERROR: arg2 must be a valid 16-bit hex value\n");
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30 return;
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31 }
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32 fb_spca_write(addr, data);
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33 }
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34
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35 void
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36 cmd_spcainit()
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37 {
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38 /*
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39 * Apparently we have to give it a reset pulse, then immediately
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40 * do the black magic register write sequence.
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41 */
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42 GPIO_OUT_REG = 0x0000;
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43 GPIO_OUT_REG = 0x0012;
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44 /* non-understandable voodoo copied from OsmocomBB */
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45 fb_spca_write(0x7e, 0x00); /* internal register access */
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46 osmo_delay_ms(10);
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47 fb_spca_write(0x7a, 0x00); /* keep CPU in reset state */
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48 osmo_delay_ms(10);
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49 fb_spca_write(0x7f, 0x00); /* select main page */
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50 osmo_delay_ms(5);
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51 fb_spca_write(0x72, 0x07); /* don't reshape timing, 16 bit mode */
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52 fb_spca_write(0x14, 0x03);
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53 fb_spca_write(0x7f, 0x00); /* select main page */
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54 osmo_delay_ms(5);
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55 fb_spca_write(0x06, 0xff);
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56 fb_spca_write(0x7f, 0x09);
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57 fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */
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58 fb_spca_write(0x23, 0x18);
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59 }
77
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60
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61 enum s6b33b1x_cmdflag { CMD, DATA, END };
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62
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63 struct s6b33b1x_cmdlist {
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64 enum s6b33b1x_cmdflag is_cmd:8; /* 1: is a command, 0: is data, 2: end marker! */
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65 u_char data; /* 8 bit to send to LC display */
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66 };
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67
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68 static const struct s6b33b1x_cmdlist
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69 s6b33b1x_initdata[] = {
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70 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */
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71 { DATA, 0x00 }, /* DATA: everything off */
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72 { CMD, 0x02 }, /* CMD Oscillation Mode Set */
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73 { DATA, 0x00 }, /* DATA: oscillator off */
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74 { CMD, 0x2c }, /* CMD Standby Mode off */
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75 { CMD, 0x50 }, /* CMD Display off */
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76 { CMD, 0x02 }, /* CMD Oscillation Mode Set */
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77 { DATA, 0x01 }, /* DATA: oscillator on */
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78 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */
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79 { DATA, 0x01 }, /* DATA: Booster 1 on */
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80 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */
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81 { DATA, 0x09 }, /* DATA: Booster 1 on, OP-AMP on */
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82 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */
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83 { DATA, 0x0b }, /* DATA: Booster 1 + 2 on, OP-AMP on */
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84 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */
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85 { DATA, 0x0f }, /* DATA: Booster 1 + 2 + 3 on, OP-AMP on */
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86 { CMD, 0x20 }, /* CMD DC-DC Select */
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87 { DATA, 0x01 }, /* DATA: step up x1.5 */
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88 { CMD, 0x24 }, /* CMD DCDC Clock Division Set */
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89 { DATA, 0x0a }, /* DATA: fPCK = fOSC/6 */
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90 { CMD, 0x2a }, /* CMD Contrast Control */
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91 { DATA, 0x2d }, /* DATA: default contrast */
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92 { CMD, 0x30 }, /* CMD Adressing mode set */
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93 { DATA, 0x0b }, /* DATA: 65536 color mode */
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94 { CMD, 0x10 }, /* CMD Driver output mode set */
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95 { DATA, 0x03 }, /* DATA: Display duty: 1/132 */
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96 { CMD, 0x34 }, /* CMD N-line inversion set */
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97 { DATA, 0x88 }, /* DATA: inversion on, one frame, every 8 blocks */
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98 { CMD, 0x40 }, /* CMD Entry mode set */
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99 { DATA, 0x00 }, /* DATA: Y address counter mode */
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100 { CMD, 0x28 }, /* CMD Temperature Compensation set */
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101 { DATA, 0x01 }, /* DATA: slope -0.05%/degC */
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102 { CMD, 0x32 }, /* CMD ROW vector mode set */
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103 { DATA, 0x01 }, /* DATA: every 2 subgroup */
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104 { CMD, 0x51 }, /* CMD Display on */
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105 { END, 0x00 }, /* MARKER: end of list */
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106 };
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107
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108 static void
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109 fb_s6b33b1x_send_cmdlist(p)
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110 struct s6b33b1x_cmdlist *p;
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111 {
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112 while(p->is_cmd != END) {
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113 nCS4_ADDR0 = p->data;
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114 p++;
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115 }
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116 }
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117
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118 void
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119 cmd_lcdinit()
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120 {
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121 GPIO_OUT_REG |= 0x0080;
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122 fb_s6b33b1x_send_cmdlist(s6b33b1x_initdata);
fcbe1332b197 pirexplore: LCD init and BL control work now
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 76
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123 }