FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/clkm.c @ 346:fdeea3d6582d
OSL: reconstruction of os_isr.c (_fl only) started
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Wed, 07 May 2014 19:50:01 +0000 |
parents | afceeeb2cba1 |
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1 /****************************************************************************** |
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 |
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 product is protected under copyright law and trade secret law as an |
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
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8 rights reserved. |
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9 |
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10 |
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11 Filename : clkm.c |
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12 |
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13 Description : Set of functions useful to test the Saturn |
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14 CLKM peripheral |
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15 |
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16 Project : drivers |
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17 |
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18 Author : pmonteil@tif.ti.com Patrice Monteil. |
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19 |
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20 Version number : 1.11 |
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21 |
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22 Date and time : 10/23/01 14:43:31 |
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23 |
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24 Previous delta : 10/23/01 14:43:31 |
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25 |
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26 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.c |
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27 |
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28 Sccs Id (SID) : '@(#) clkm.c 1.11 10/23/01 14:43:31 ' |
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29 |
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30 |
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31 |
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32 *****************************************************************************/ |
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33 |
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34 //############################################################ |
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35 //############################################################ |
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36 //### Be careful: this file must be placed in Flash Memory ### |
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37 //### and compiled in 16 bits length intructions ### |
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38 //### (CF. the function wait_ARM_cycles() ### |
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39 //############################################################ |
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40 //############################################################ |
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41 |
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42 #include "../include/config.h" |
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43 #include "../include/sys_types.h" |
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44 |
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45 #include "mem.h" |
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46 #include "clkm.h" |
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47 |
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48 static SYS_UWORD32 ratio_wait_loop = 0; |
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49 |
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50 #if (CHIPSET == 12) |
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51 const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE] = {1, 1.5, 2, 3}; |
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52 #endif |
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53 |
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54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
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55 /*---------------------------------------------------------------/ |
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56 /* CLKM_InitARMClock() */ |
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57 /*--------------------------------------------------------------*/ |
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58 /* Parameters : clk_src : 0x00 means DPLL selected */ |
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59 /* 0x01 means VTCX0 selected */ |
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60 /* 0x03 means CLKIN selected */ |
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61 /* clk_xp5 : Enable 1.5 or 2.5 division factor */ |
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62 /* (0 or 1) */ |
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63 /* clk_div : Division factor applied to clock */ |
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64 /* source */ |
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65 /* WARNING : reverse order in comparison to ULYSSE */ |
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66 /* */ |
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67 /* Return : none */ |
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68 /* Functionality :Initialize the ARM Clock frequency */ |
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69 /*--------------------------------------------------------------*/ |
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70 |
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71 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5) |
93
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72 { |
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73 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK; |
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74 |
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75 cntl &= ~(CLKM_CLKIN0 | CLKM_CLKIN_SEL | CLKM_ARM_MCLK_XP5 | CLKM_MCLK_DIV); |
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76 |
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77 cntl |= ((clk_src << 1) | (clk_xp5 << 3) | (clk_div << 4)); |
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78 |
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79 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl; |
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80 } |
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81 #else |
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82 /*---------------------------------------------------------------/ |
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83 /* CLKM_InitARMClock() */ |
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84 /*--------------------------------------------------------------*/ |
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85 /* Parameters : clk_src : 0x00 means CLKIN selected */ |
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86 /* 0x01 means 32 K selected */ |
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87 /* 0x02 means External clock selected */ |
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88 /* */ |
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89 /* Return : none */ |
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90 /* Functionality :Initialize the ARM Clock frequency */ |
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91 /*--------------------------------------------------------------*/ |
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92 |
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93 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div) |
93
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94 { |
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95 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK; |
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96 |
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97 cntl &= ~(CLKM_LOW_FRQ | CLKM_CLKIN_SEL | CLKM_MCLK_DIV); |
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98 |
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99 cntl |= ((clk_src << 1) | (clk_div << 4)); |
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100 |
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101 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl; |
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102 } |
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103 |
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104 #endif |
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105 |
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106 |
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107 /*-------------------------------------------------------*/ |
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108 /* convert_nanosec_to_cycles() */ |
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109 /*-------------------------------------------------------*/ |
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110 /* parameter: time in 10E-9 seconds */ |
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111 /* return: Number of cycles for the wait_ARM_cycles() */ |
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112 /* function */ |
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113 /* */ |
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114 /* Description: */ |
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115 /* ------------ */ |
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116 /* convert x nanoseconds in y cycles used by the ASM loop*/ |
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117 /* function . Before calling this function, call the */ |
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118 /* initialize_wait_loop() function */ |
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119 /* Called when the HardWare needs time to wait */ |
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120 /*-------------------------------------------------------*/ |
111
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121 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time) |
93
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122 { |
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123 return( time / ratio_wait_loop); |
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124 } |
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125 |
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126 |
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127 /*-------------------------------------------------------*/ |
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128 /* initialize_wait_loop() */ |
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129 /*-------------------------------------------------------*/ |
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130 /* */ |
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131 /* Description: */ |
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132 /* ------------ */ |
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133 /* Init the ratio used to convert time->Cycles according */ |
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134 /* to hardware parameters */ |
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135 /* measurement time for this function (ARM 39Mhz, 3 waits*/ |
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136 /* states) = 75 micoseconds */ |
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137 /*-------------------------------------------------------*/ |
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138 |
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139 void initialize_wait_loop(void) |
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140 { |
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141 #define NBR_CYCLES_IN_LOOP 5 // this value is got from an oscilloscope measurement |
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142 |
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143 double src_ratio; |
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144 double final_ratio; |
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145 |
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146 SYS_UWORD16 flash_access_size; |
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147 SYS_UWORD16 flash_wait_state; |
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148 SYS_UWORD32 nbr; |
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149 SYS_UWORD32 arm_clock; |
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150 |
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151 ////////////////////////////////// |
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152 // compute the ARM clock used // |
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153 ////////////////////////////////// |
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154 { |
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155 SYS_UWORD16 arm_mclk_xp5; |
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156 SYS_UWORD16 arm_ratio; |
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157 SYS_UWORD16 clk_src; |
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158 SYS_UWORD16 clkm_cntl_arm_clk_reg = * (volatile SYS_UWORD16 *) CLKM_CNTL_ARM_CLK; |
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159 |
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160 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
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161 clk_src = (clkm_cntl_arm_clk_reg & MASK_CLKIN) >> 1; |
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162 switch (clk_src) |
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163 { |
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164 case 0x00: //DPLL selected |
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165 // select the DPLL factor |
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166 if (((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK) != 0) |
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167 { |
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168 SYS_UWORD16 dpll_div; |
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169 SYS_UWORD16 dpll_mul; |
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170 |
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171 dpll_div=DPLL_READ_DPLL_DIV; |
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172 dpll_mul=DPLL_READ_DPLL_MUL; |
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173 src_ratio = (double)(dpll_mul)/(double)(dpll_div+1); |
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174 } |
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175 else // DPLL in bypass mode |
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176 { |
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177 SYS_UWORD16 dpll_div = DPLL_BYPASS_DIV; |
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178 src_ratio= (double)(1)/(double)(dpll_div+1); |
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179 } |
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180 break; |
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181 case 0x01: //VTCX0 selected |
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182 src_ratio = 1; |
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183 break; |
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184 case 0x03: //CLKIN selected (external clock) |
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185 src_ratio = 1; |
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186 break; |
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187 } |
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188 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL) |
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189 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4; |
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190 |
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191 // check if the 1.5 or 2.5 division factor is enabled |
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192 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & CLKM_ARM_MCLK_XP5; |
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193 |
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194 if (arm_mclk_xp5 == 0) // division factor enable for ARM clock ? |
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195 { |
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196 if (arm_ratio == 0) |
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197 arm_ratio =1; |
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198 } |
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199 else |
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200 arm_ratio = ((arm_ratio>>1) & 0x0001) == 0 ? 1.5 : 2.5; |
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201 |
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202 |
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203 #else // CHIPSET |
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204 src_ratio = 1; |
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205 |
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206 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL) |
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207 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4; |
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208 |
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209 // check if the 1.5 or 2.5 division factor is enabled |
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210 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & MASK_ARM_MCLK_1P5; |
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211 |
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212 if (arm_mclk_xp5 == 1) // division factor enable for ARM clock ? |
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213 arm_ratio = 1.5; |
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214 else |
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215 { |
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216 if (arm_ratio == 0) |
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217 arm_ratio = 4; |
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218 else |
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219 if (arm_ratio == 1 ) |
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220 arm_ratio = 2; |
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221 else |
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222 arm_ratio = 1; |
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223 } |
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224 |
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225 #endif // CHIPSET |
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226 |
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227 final_ratio = (src_ratio / (double) arm_ratio); |
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228 |
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229 } |
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230 ////////////////////////////////////////// |
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231 // compute the Flash wait states used // |
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232 ////////////////////////////////////////// |
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233 |
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234 #if (CHIPSET == 12) |
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235 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS5); |
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236 #else |
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237 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS0); |
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238 #endif |
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239 flash_access_size = (flash_access_size >> 5) & 0x0003; // 0=>8bits, 1=>16 bits, 2 =>32 bits |
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240 |
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241 // the loop file is compiled in 16 bits it means |
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242 // flash 8 bits => 2 loads for 1 16 bits assembler instruction |
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243 // flash 16 bits => 1 loads for 1 16 bits assembler instruction |
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244 // flash 32 bits => 1 loads for 1 16 bits assembler instruction (ARM bus 16 bits !!) |
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245 |
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246 // !!!!!!!!! be careful: if this file is compile in 32 bits, change these 2 lines here after !!! |
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247 if (flash_access_size == 0) flash_access_size = 2; |
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248 else flash_access_size = 1; |
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249 |
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250 #if (CHIPSET == 12) |
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251 /* |
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252 * WARNING - New ARM Memory Interface features are not supported here below (Page Mode, extended WS, Dummy Cycle,...). |
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253 */ |
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254 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS5); |
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255 #else |
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256 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS0); |
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257 #endif |
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258 flash_wait_state &= 0x001F; |
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259 |
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260 ////////////////////////////////////// |
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261 // compute the length of the loop // |
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262 ////////////////////////////////////// |
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263 |
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264 // Number of flash cycles for the assembler loop |
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265 nbr = NBR_CYCLES_IN_LOOP; |
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266 |
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267 // Number of ARM cycles for the assembler loop |
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268 nbr = nbr * (flash_wait_state + 1) * (flash_access_size); |
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269 |
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270 // time for the assembler loop (unit nanoseconds: 10E-9) |
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271 arm_clock = final_ratio * 13; // ARM clock in Mhz |
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272 ratio_wait_loop = (SYS_UWORD32)((nbr*1000) / arm_clock); |
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273 } |
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274 |
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275 |
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276 /*-------------------------------------------------------*/ |
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277 /* wait_ARM_cycles() */ |
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278 /*-------------------------------------------------------*/ |
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279 /* */ |
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280 /* Description: */ |
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281 /* ------------ */ |
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282 /* Called when the HardWare needs time to wait. */ |
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283 /* this function wait x cycles and is used with the */ |
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284 /* convert_nanosec_to_cycles() & initialize_wait_loop() */ |
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285 /* */ |
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286 /* Exemple: wait 10 micro seconds: */ |
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287 /* initialize_wait_loop(); */ |
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288 /* wait_ARM_cycles(convert_nanosec_to_cycles(10000)) */ |
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289 /* */ |
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290 /* minimum time value with cpt_loop = 0 (estimated) */ |
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291 /* and C-SAMPLE / flash 6,5Mhz ~ 1,5 micro seconds */ |
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292 /* */ |
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293 /* */ |
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294 /* Be careful : in order to respect the rule about the */ |
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295 /* conversion "time => number of cylcles in this loop" */ |
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296 /* (Cf the functions: convert_nanosec_to_cycles() and */ |
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297 /* initialize_wait_loop() ) respect the following rules: */ |
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298 /* This function must be placed in Flash Memory and */ |
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299 /* compiled in 16 bits instructions length */ |
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300 /*-------------------------------------------------------*/ |
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301 void wait_ARM_cycles(SYS_UWORD32 cpt_loop) |
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302 { |
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303 // C code: |
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304 // while (cpt_loop -- != 0); |
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305 |
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306 asm(" CMP A1, #0"); |
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307 asm(" BEQ END_FUNCTION"); |
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308 |
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309 asm("LOOP_LINE: "); |
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310 asm(" SUB A1, A1, #1"); |
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311 asm(" CMP A1, #0"); |
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312 asm(" BNE LOOP_LINE"); |
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313 |
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314 asm("END_FUNCTION: "); |
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315 } |