FreeCalypso > hg > freecalypso-sw

annotate gsm-fw/bsp/oldint.S @ 518:ffbb71ee664c

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gsm-fw/L1/cust0/ind_os.c: adopted MV100 version, started FC adaptation
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Thu, 10 Jul 2014 07:21:49 +0000
parents afceeeb2cba1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
130
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
1 /*
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
2 * This module contains that part of TI's int.s (INT_Initialize) code
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
3 * which does some entry-point initialization of a few Calypso registers.
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
4 * The important part for us is getting rid of whatever PLL setup
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
5 * may have been done by the BootROM-based process that got us loaded
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
6 * and running - we need to do that before we can do our own setup.
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
7 */
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
8
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
9 .code 32
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
10 .text
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
11
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
12 #define CNTL_ARM_CLK_REG 0xFFFFFD00 // CNTL_ARM_CLK register address
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
13 #define DPLL_CNTRL_REG 0xFFFF9800 // DPLL control register address
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
14 #define EXTRA_CONTROL_REG 0xFFFFFB10 // Extra Control register CONF addr
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
15 #define MPU_CTL_REG 0xFFFFFF08 // MPU_CTL register address
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
16
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
17 #define CNTL_ARM_CLK_RST 0x1081 // Init of CNTL_ARM_CLK register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
18
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
19 // Use DPLL, Divide by 1
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
20 #define DPLL_CONTROL_RST 0x2002 // Configure DPLL in default state
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
21 #define DISABLE_DU_MASK 0x0800 // Mask to Disable the DU module
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
22 #define ENABLE_DU_MASK 0xF7FF // Mask to Enable the DU module
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
23 #define MPU_CTL_RST 0x0000 // Reset value of MPU_CTL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
24 // - All protections disabled
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
25
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
26 .globl freecalypso_disable_bootrom_pll
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
27 freecalypso_disable_bootrom_pll:
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
28 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
29 @ Configure DPLL register with reset value
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
30 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
31 ldr r1,=DPLL_CNTRL_REG @ Load address of DPLL register in R1
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
32 ldrh r2,=DPLL_CONTROL_RST @ Load DPLL reset value in R2
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
33 strh r2,[r1] @ Store DPLL reset value in DPLL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
34
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
35 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
36 @ Wait that DPLL goes in BYPASS mode
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
37 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
38 Wait_DPLL_Bypass:
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
39 ldr r2,[r1] @ Load DPLL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
40 and r2,r2,#1 @ Perform a mask on bit 0
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
41 cmp r2,#1 @ Compare DPLL lock bit
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
42 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
43
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
44 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
45 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
46 @ generate ARM clock with division factor of 1.
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
47 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
48 ldr r1,=CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
49 ldrh r2,=CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
50 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
51
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
52 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
53 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
54 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
55 ldr r1,=EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
56 @ ldrh r2,=DISABLE_DU_MASK @ Load mask to write in Extra Control register CONF
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
57 ldrh r2,=ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
58 ldrh r0,[r1] @ Load Extra Control register CONF in r0
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
59 @ orr r0,r0,r2 @ Disable DU module
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
60 and r0,r0,r2 @ Enable DU module
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
61 strh r0,[r1] @ Store configuration in Extra Control register CONF
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
62
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
63 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
64 @ Disable all MPU protections
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
65 @
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
66 ldr r1,=MPU_CTL_REG @ Load address of MPU_CTL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
67 ldrh r2,=MPU_CTL_RST @ Load reset value of MPU_CTL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
68 strh r2,[r1] @ Store reset value of MPU_CTL register
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
69
8b0793c67f9f nuc-fw: final preparations for the big transition
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
70 bx lr