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comparison gsm-fw/L1/cfile/l1_pwmgr.c @ 566:065bf2b63a95

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L1: started work on l1_pwmgr.c
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 08 Aug 2014 05:32:56 +0000
parents 67ab5f240b7d
children 528fa901ae79
comparison
equal deleted inserted replaced
565:335f9b00f8fc 566:065bf2b63a95
4 * 4 *
5 * Filename l1_pwmgr.c 5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9
9 // pinghua add these programe code section to put some sleep code into internal ram. 10 // pinghua add these programe code section to put some sleep code into internal ram.
11 /*
12 * FreeCalypso: the Leonardo binary object version puts all of l1_pwmgr
13 * into the regular run-from-flash text section, so we'll do the same
14 * for now.
15 */
16 #if 0
10 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf") 17 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf")
11 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf") 18 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf")
12 #pragma CODE_SECTION(audio_madc_sleep,".emifconf") 19 #pragma CODE_SECTION(audio_madc_sleep,".emifconf")
13 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf") 20 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf")
14 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf") 21 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf")
27 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf") 34 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf")
28 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf") 35 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf")
29 #pragma CODE_SECTION(l1s_gauging_task,".emifconf") 36 #pragma CODE_SECTION(l1s_gauging_task,".emifconf")
30 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf") 37 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf")
31 // 2-03-2007 pinghua added end 38 // 2-03-2007 pinghua added end
39 #endif
40
32 #define L1_PWMGR_C 41 #define L1_PWMGR_C
33 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START 42 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
43
44 #include "config.h"
45 #include "l1_confg.h"
34 46
35 //sajal added ..................................... 47 //sajal added .....................................
36 #if (CODE_VERSION == SIMULATION) 48 #if (CODE_VERSION == SIMULATION)
37 //#include "l1_pwmgr.h" 49 //#include "l1_pwmgr.h"
38 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8; 50 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8;
63 #endif 75 #endif
64 //sajal added till here...... 76 //sajal added till here......
65 77
66 78
67 79
68 #include "timer/timer2.h" 80 #include "../../bsp/timer2.h"
69 #include "armio/armio.h" 81 #include "../../bsp/armio.h"
70 82 #include "../../serial/serialswitch.h"
71 //omaps00090550 #include "l1_macro.h" 83
72 #include "l1_confg.h" 84 #if 0 //(OP_L1_STANDALONE == 0)
73
74 #if (OP_L1_STANDALONE == 1)
75 #include "uart/serialswitch_core.h"
76 #else
77 #include "uart/serialswitch.h"
78 #endif
79
80 #if (OP_L1_STANDALONE == 0)
81 #include "sim/sim.h" 85 #include "sim/sim.h"
82 #include "rv_swe.h" 86 #include "rv_swe.h"
83 #endif 87 #endif
84 88
85 89
160 164
161 165
162 #include "l1_types.h" 166 #include "l1_types.h"
163 #include "l1_const.h" 167 #include "l1_const.h"
164 168
165 #include "abb/abb.h" 169 #include "../../bsp/abb+spi/abb.h"
166 #include "dma/sys_dma.h" 170 /* #include "dma/sys_dma.h" */
167 171
168 #if (OP_BT == 1) 172 #if (OP_BT == 1)
169 #include "hci_ll_simul.h" 173 #include "hci_ll_simul.h"
170 #endif 174 #endif
171 175
198 #include "l1_defty.h" 202 #include "l1_defty.h"
199 #include "l1_varex.h" 203 #include "l1_varex.h"
200 #include "l1_tabs.h" 204 #include "l1_tabs.h"
201 #include "sys_types.h" 205 #include "sys_types.h"
202 #include "tpudrv.h" 206 #include "tpudrv.h"
203 #include "cust_os.h" 207 #include "../../gpf/inc/cust_os.h"
204 #include "l1_msgty.h" 208 #include "l1_msgty.h"
205 #include "l1_proto.h" 209 #include "l1_proto.h"
206 #include "l1_trace.h" 210 #include "l1_trace.h"
207 #include "timer/timer.h" 211 #include "../../bsp/timer.h"
208 212
209 213
210 #if (CHIPSET == 12) || (CHIPSET == 15) 214 #if (CHIPSET == 12) || (CHIPSET == 15)
211 #include "timer/timer_sec.h" 215 #include "timer/timer_sec.h"
212 #include "inth/sys_inth.h" 216 #include "inth/sys_inth.h"
332 336
333 #endif // omaps00090550 #14 -d removal (CHIPSET = 15) 337 #endif // omaps00090550 #14 -d removal (CHIPSET = 15)
334 338
335 339
336 #else //(CHIPSET == 12) || (CHIPSET == 15) 340 #else //(CHIPSET == 12) || (CHIPSET == 15)
337 #include "inth/iq.h" 341 #include "../../bsp/iq.h"
338 #include "inth/inth.h" 342 #include "../../bsp/inth.h"
339 #endif 343 #endif
340 // #include "timer1.h" 344 // #include "timer1.h"
341 #include "ulpd/ulpd.h" 345 #include "../../bsp/ulpd.h"
342 #include "clkm/clkm.h" 346 #include "../../bsp/clkm.h"
343 #include "memif/mem.h" 347 #include "../../bsp/mem.h"
344 #if L2_L3_SIMUL 348 #if L2_L3_SIMUL
345 #include "hw_debug.h" 349 #include "hw_debug.h"
346 #endif 350 #endif
347 351
348 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) 352 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
358 #else 362 #else
359 #include "csmi/csmi.h" 363 #include "csmi/csmi.h"
360 #endif 364 #endif
361 #endif 365 #endif
362 366
367 #if (CHIPSET == 15)
363 #include "drp_api.h" 368 #include "drp_api.h"
369 #endif
364 370
365 #endif // NO SIMULATION 371 #endif // NO SIMULATION
366 372
367 #if (CODE_VERSION != SIMULATION) 373 #if (CODE_VERSION != SIMULATION)
368 // for PTOOL compatibility 374 // for PTOOL compatibility
399 405
400 #if (GSM_IDLE_RAM != 0) 406 #if (GSM_IDLE_RAM != 0)
401 extern void l1s_trace_mftab(void); 407 extern void l1s_trace_mftab(void);
402 #endif 408 #endif
403 409
404 #if (CODE_VERSION != SIMULATION) 410 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
405 extern T_DRP_REGS_STR *drp_regs; 411 extern T_DRP_REGS_STR *drp_regs;
406 #endif 412 #endif
407 413
408 #if L1_GPRS 414 #if L1_GPRS
409 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void); 415 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void);
455 #endif // NOT SIMULATION 461 #endif // NOT SIMULATION
456 462
457 #if(CHIPSET == 15) 463 #if(CHIPSET == 15)
458 464
459 /************************************************************/ 465 /************************************************************/
460 /* Configure EMIF for optimal consumption */ 466 /* Configure EMIF for optimal consumption */
461 /************************************************************/ 467 /************************************************************/
462 468
463 469
464 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en) 470 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en)
465 { 471 {
1537 #else 1543 #else
1538 UWORD32 sleep_time = l1s.actual_time.fn; 1544 UWORD32 sleep_time = l1s.actual_time.fn;
1539 #endif 1545 #endif
1540 1546
1541 #if(CHIPSET == 15) 1547 #if(CHIPSET == 15)
1542 Uint8 sleep_status; 1548 Uint8 sleep_status;
1543 #endif 1549 #endif
1544 1550
1545 #if (GSM_IDLE_RAM != 0) 1551 #if (GSM_IDLE_RAM != 0)
1546 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl; 1552 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1547 BOOL flag_traffic_controller_state = 0; 1553 BOOL flag_traffic_controller_state = 0;
1623 { 1629 {
1624 OS_system_Unprotect(); 1630 OS_system_Unprotect();
1625 // free System structure 1631 // free System structure
1626 // Enable all IRQ 1632 // Enable all IRQ
1627 //l1_pwmgr_irq_dis_flag = 0; 1633 //l1_pwmgr_irq_dis_flag = 0;
1628 #if (CODE_VERSION!=SIMULATION) 1634 #if (CODE_VERSION!=SIMULATION)
1629 INT_EnableIRQ(); 1635 INT_EnableIRQ();
1630 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); 1636 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1631 #endif 1637 #endif
1632 #if (GSM_IDLE_RAM != 0) 1638 #if (GSM_IDLE_RAM != 0)
1633 gsm_idle_ram_ctl->os_load = 0; 1639 gsm_idle_ram_ctl->os_load = 0;
1634 gsm_idle_ram_ctl->hw_timer = 0; 1640 gsm_idle_ram_ctl->hw_timer = 0;
1635 #endif // GSM_IDLE_RAM 1641 #endif // GSM_IDLE_RAM
1636 return; 1642 return;
1642 #endif 1648 #endif
1643 //================================================= 1649 //=================================================
1644 // check OS loading 1650 // check OS loading
1645 //================================================= 1651 //=================================================
1646 OSload = OS_get_inactivity_ticks(); 1652 OSload = OS_get_inactivity_ticks();
1647 #if (CODE_VERSION!=SIMULATION) 1653 #if (CODE_VERSION!=SIMULATION)
1648 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){ 1654 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
1649 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD; 1655 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
1650 l1_pwmgr_debug.fail_ret_val = OSload; 1656 l1_pwmgr_debug.fail_ret_val = OSload;
1651 } 1657 }
1652 #endif //NOT SIMULATION 1658 #endif //NOT SIMULATION
1653 1659
1654 //================================================= 1660 //=================================================
1655 // check HW Timers loading 1661 // check HW Timers loading
1656 //================================================= 1662 //=================================================
1657 HWtimer= l1s_get_HWTimers_ticks(); 1663 HWtimer= l1s_get_HWTimers_ticks();
1714 { 1720 {
1715 1721
1716 1722
1717 1723
1718 #if (OP_L1_STANDALONE == 0) 1724 #if (OP_L1_STANDALONE == 0)
1719 /*GC_Wakeup(); OMAPS00134004*/ 1725 /*GC_Wakeup(); OMAPS00134004*/
1720 #endif 1726 #endif
1721 1727
1722 #if (CODE_VERSION != SIMULATION) 1728 #if (CODE_VERSION != SIMULATION)
1723 OS_system_Unprotect(); 1729 OS_system_Unprotect();
1724 // free System structure 1730 // free System structure
1739 #endif 1745 #endif
1740 1746
1741 #if (CHIPSET != 15) 1747 #if (CHIPSET != 15)
1742 SER_WakeUpUarts(); // Wake up Uarts 1748 SER_WakeUpUarts(); // Wake up Uarts
1743 #else 1749 #else
1744 // To be checked if this needs a change 1750 // To be checked if this needs a change
1745 #endif 1751 #endif
1746 1752
1747 #if (GSM_IDLE_RAM != 0) 1753 #if (GSM_IDLE_RAM != 0)
1748 // The traffic controller state shall be restored as it was before 1754 // The traffic controller state shall be restored as it was before
1749 // calling SER_WakeUpUarts. Do not disable it if an interrup occured 1755 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1804 #if (CHIPSET == 12) || (CHIPSET == 15) 1810 #if (CHIPSET == 12) || (CHIPSET == 15)
1805 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) && 1811 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1806 !CLKM_READ_nIDLE3) 1812 !CLKM_READ_nIDLE3)
1807 #else 1813 #else
1808 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) 1814 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
1809 #endif 1815 #endif
1810 #endif 1816 #endif
1811 l1s.pw_mgr.sleep_performed = CLOCK_STOP; 1817 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
1812 else 1818 else
1813 { 1819 {
1814 // BIG SLEEP is chosen : check the reason 1820 // BIG SLEEP is chosen : check the reason
1943 1949
1944 #endif // NOT SIMULATION 1950 #endif // NOT SIMULATION
1945 if(!sleep_status) 1951 if(!sleep_status)
1946 { 1952 {
1947 1953
1948 #if (OP_L1_STANDALONE == 0) 1954 #if (OP_L1_STANDALONE == 0)
1949 /*GC_Wakeup(); OMAPS00134004*/ 1955 /*GC_Wakeup(); OMAPS00134004*/
1950 #endif 1956 #endif
1951 1957
1952 #if (CODE_VERSION != SIMULATION) 1958 #if (CODE_VERSION != SIMULATION)
1953 OS_system_Unprotect(); 1959 OS_system_Unprotect();
1954 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); 1960 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1955 #endif // NOT SIMULATION 1961 #endif // NOT SIMULATION
1990 #if (CODE_VERSION != SIMULATION) 1996 #if (CODE_VERSION != SIMULATION)
1991 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 1997 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1992 { 1998 {
1993 // ==== STop RF and TPU..... =================== 1999 // ==== STop RF and TPU..... ===================
1994 2000
1995 //L1_trace_string("Proceeding to Deep Sleep\n"); 2001 //L1_trace_string("Proceeding to Deep Sleep\n");
1996 2002
1997 2003
1998 l1dmacro_RF_sleep(); 2004 l1dmacro_RF_sleep();
1999 2005
2000 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET | 2006 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
2056 2062
2057 //============================================== 2063 //==============================================
2058 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) 2064 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
2059 //============================================== 2065 //==============================================
2060 #if (ANALOG != 11) 2066 #if (ANALOG != 11)
2061 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc,l1s.pw_mgr.afc_bypass_mode); 2067 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
2062 #else 2068 #else
2063 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS 2069 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS
2064 #endif 2070 #endif
2065 2071
2066 #if (OP_BT == 1) 2072 #if (OP_BT == 1)
2068 #endif 2074 #endif
2069 //================================================= 2075 //=================================================
2070 // STop SPI ..... 2076 // STop SPI .....
2071 //================================================= 2077 //=================================================
2072 2078
2073 #if(CHIPSET != 15) 2079 #if(CHIPSET != 15)
2074 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED 2080 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
2075 #endif 2081 #endif
2076 #endif // NOT SIMULATION 2082 #endif // NOT SIMULATION
2077 2083
2078 2084
2079 //================================================= 2085 //=================================================
2080 // CQ19599: For Calypso+ chipset, extended page mode 2086 // CQ19599: For Calypso+ chipset, extended page mode
2101 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) 2107 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
2102 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2108 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2103 { 2109 {
2104 // DEEP SLEEP -> need time to setup afc and rf 2110 // DEEP SLEEP -> need time to setup afc and rf
2105 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration; 2111 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration;
2106 #if (CODE_VERSION == NOT_SIMULATION) 2112 #if (CODE_VERSION == NOT_SIMULATION)
2107 // Sleep one more TDMA - this is done as part of merging init and TPU control 2113 // Sleep one more TDMA - this is done as part of merging init and TPU control
2108 wake_up_time += 1; 2114 wake_up_time += 1;
2109 #endif 2115 #endif
2110 2116
2111 } 2117 }
2112 else 2118 else
2113 // BIG SLEEP 2119 // BIG SLEEP
2114 wake_up_time = min_time - 1; 2120 wake_up_time = min_time - 1;
2191 2197
2192 //========================================================== 2198 //==========================================================
2193 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized 2199 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
2194 //========================================================== 2200 //==========================================================
2195 2201
2196 #if(CHIPSET != 15) 2202 #if(CHIPSET != 15)
2197 UWORD16 clocks_stopped; //OMAPS90550- new 2203 UWORD16 clocks_stopped; //OMAPS90550- new
2198 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status); 2204 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2199 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT) 2205 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2200 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN); 2206 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
2201 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT) 2207 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2202 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001); 2208 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
2203 #else 2209 #else
2204 // Nothing to be done as it is taken care by Locosto_Configure_BS 2210 // Nothing to be done as it is taken care by Locosto_Configure_BS
2205 #endif 2211 #endif
2206 2212
2207 #if (W_A_CALYPSO_BUG_01435 == 1) 2213 #if (W_A_CALYPSO_BUG_01435 == 1)
2208 f_arm_sleep_cmd(BIG_SLEEP); 2214 f_arm_sleep_cmd(BIG_SLEEP);
2209 #else 2215 #else
2210 2216
2235 #if (GSM_IDLE_RAM_DEBUG == 1) 2241 #if (GSM_IDLE_RAM_DEBUG == 1)
2236 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1 2242 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
2237 #endif 2243 #endif
2238 2244
2239 2245
2240 l1s_wakeup(); 2246 l1s_wakeup();
2241 2247
2242 #if (CHIPSET == 15) 2248 #if (CHIPSET == 15)
2243 // The following command writes '1' into CKM_OCPCLK register in DRP; 2249 // The following command writes '1' into CKM_OCPCLK register in DRP;
2244 // This is done after the DPLL is up 2250 // This is done after the DPLL is up
2245 // CKM_OCPCLK (R/W) = Address 0xFFFF040C 2251 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2246 // Bit 0: 0 ?OCP clock is the DCXO clock. 2252 // Bit 0: 0 ?OCP clock is the DCXO clock.
2247 // 1 ?OCP clock is the divided DSP clock 2253 // 1 ?OCP clock is the divided DSP clock
2275 //================================================= 2281 //=================================================
2276 #if (CODE_VERSION != SIMULATION) 2282 #if (CODE_VERSION != SIMULATION)
2277 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2283 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2278 { 2284 {
2279 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN; 2285 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
2280 UWORD8 local_sleep_status; 2286 UWORD8 local_sleep_status;
2281 2287
2282 2288
2283 #if (CHIPSET == 15) 2289 #if (CHIPSET == 15)
2284 2290
2285 DBB_Wakeup_DS(); 2291 DBB_Wakeup_DS();
2325 #endif 2331 #endif
2326 2332
2327 //================================================= 2333 //=================================================
2328 //if CLOCK_STOP or FRAME-STOP : ReStart SPI 2334 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
2329 //================================================= 2335 //=================================================
2330 #if(CHIPSET != 15) 2336 #if(CHIPSET != 15)
2331 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED 2337 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
2332 #endif 2338 #endif
2333 2339
2334 //================================================= 2340 //=================================================
2335 // Wake up ABB 2341 // Wake up ABB
2336 //================================================= 2342 //=================================================
2337 #if (ANALOG != 11) 2343 #if (ANALOG != 11)
2338 ABB_wakeup(l1s.pw_mgr.sleep_performed,l1s.afc,l1s.pw_mgr.afc_bypass_mode); 2344 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
2339 #else 2345 #else
2340 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS 2346 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS
2341 #endif 2347 #endif
2342 2348
2343 #if (OP_BT == 1) 2349 #if (OP_BT == 1)
2354 f_memif_extended_page_mode_enable(); 2360 f_memif_extended_page_mode_enable();
2355 #endif 2361 #endif
2356 2362
2357 #if (OP_L1_STANDALONE == 0) 2363 #if (OP_L1_STANDALONE == 0)
2358 /*GC_Wakeup(); OMAPS00134004*/ 2364 /*GC_Wakeup(); OMAPS00134004*/
2359 #endif 2365 #endif
2360 2366
2361 #if (CODE_VERSION != SIMULATION) 2367 #if (CODE_VERSION != SIMULATION)
2362 //================================================= 2368 //=================================================
2363 // enable IRQ 2369 // enable IRQ
2364 //================================================= 2370 //=================================================
2422 2428
2423 2429
2424 #if (CHIPSET != 15) 2430 #if (CHIPSET != 15)
2425 SER_WakeUpUarts(); // Wake up Uarts 2431 SER_WakeUpUarts(); // Wake up Uarts
2426 #else 2432 #else
2427 // To be checked if this needs a change 2433 // To be checked if this needs a change
2428 #endif 2434 #endif
2429 2435
2430 2436
2431 #if (GSM_IDLE_RAM != 0) 2437 #if (GSM_IDLE_RAM != 0)
2432 // The traffic controller state shall be restored as it was before 2438 // The traffic controller state shall be restored as it was before
3123 #endif 3129 #endif
3124 #endif 3130 #endif
3125 #endif 3131 #endif
3126 3132
3127 // DSP programmation ....... 3133 // DSP programmation .......
3128 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 3134 #if (DSP >= 33)
3129 #if (CHIPSET==4) 3135 #if (CHIPSET==4)
3130 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB; 3136 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
3131 #endif 3137 #endif
3132 #else 3138 #else
3133 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP 3139 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
3174 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS); 3180 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
3175 #endif 3181 #endif
3176 #endif 3182 #endif
3177 3183
3178 // DSP programmation : free IDLE modes... 3184 // DSP programmation : free IDLE modes...
3179 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 3185 #if (DSP >= 33)
3180 #if (CHIPSET==4) 3186 #if (CHIPSET==4)
3181 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB; 3187 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
3182 #endif 3188 #endif
3183 #else 3189 #else
3184 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1; 3190 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;