FreeCalypso > hg > freecalypso-sw
comparison target-utils/c139explore/uwire.c @ 952:15b1b396ad23
c139explore: OsmocomBB morons got uwire wrong, TI got it right
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
---|---|
date | Wed, 04 Nov 2015 03:51:00 +0000 |
parents | cd34e0d534b9 |
children |
comparison
equal
deleted
inserted
replaced
951:eb27543ce18e | 952:15b1b396ad23 |
---|---|
61 static inline void _uwire_wait(int mask, int val) | 61 static inline void _uwire_wait(int mask, int val) |
62 { | 62 { |
63 while ((UWIRE_REGS.reg_csr & mask) != val); | 63 while ((UWIRE_REGS.reg_csr & mask) != val); |
64 } | 64 } |
65 | 65 |
66 /* | |
67 * Let's try changing the chip select logic from OsmocomBB way | |
68 * to the way seen in TI's R2D source. | |
69 */ | |
70 | |
66 void uwire_init(void) | 71 void uwire_init(void) |
67 { | 72 { |
68 UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2; | 73 UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2; |
74 UWIRE_REGS.reg_sr1 = UWIRE_CSn_FRQ_DIV2; | |
75 #if 0 | |
69 UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2; | 76 UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2; |
70 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD; | 77 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD; |
71 _uwire_wait(UWIRE_CSR_CSRB, 0); | 78 _uwire_wait(UWIRE_CSR_CSRB, 0); |
79 #endif | |
72 } | 80 } |
73 | 81 |
74 send_via_uwire(word) | 82 send_via_uwire(word) |
75 unsigned word; | 83 unsigned word; |
76 { | 84 { |
77 u16 tmp = 0; | 85 #if 0 |
78 | |
79 /* select the chip */ | 86 /* select the chip */ |
80 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD; | 87 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD; |
81 _uwire_wait(UWIRE_CSR_CSRB, 0); | 88 _uwire_wait(UWIRE_CSR_CSRB, 0); |
89 #endif | |
82 | 90 |
83 UWIRE_REGS.reg_data = word << 7; | 91 UWIRE_REGS.reg_data = word << 7; |
84 UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START; | 92 UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START |
93 | UWIRE_CSR_CS_CMD; | |
85 _uwire_wait(UWIRE_CSR_CSRB, 0); | 94 _uwire_wait(UWIRE_CSR_CSRB, 0); |
86 | 95 |
87 /* unselect the chip */ | 96 /* unselect the chip */ |
88 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0; | 97 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0; |
98 #if 0 | |
89 _uwire_wait(UWIRE_CSR_CSRB, 0); | 99 _uwire_wait(UWIRE_CSR_CSRB, 0); |
100 #endif | |
90 | 101 |
91 return 0; | 102 return 0; |
92 } | 103 } |