FreeCalypso > hg > freecalypso-sw
comparison nuc-fw/sysglue/irqfiq.S @ 114:17b0511b243c
nuc-fw: continuing lowest-level BSP integration
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Thu, 24 Oct 2013 02:47:14 +0000 |
| parents | |
| children | 2c5160a9d652 |
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| 113:3b2e941043d8 | 114:17b0511b243c |
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| 1 /* | |
| 2 * This module contains the assembly shells for IRQ and FIQ, separated | |
| 3 * from the architectured vectors only by some simple unconditional | |
| 4 * branch instructions. | |
| 5 * | |
| 6 * Note that TI's way of handling interrupts sacrifices Nucleus' ability | |
| 7 * to nest interrupts and minimize the IRQ-disabled window: if my (Falcon's) | |
| 8 * understanding is correct, TI's code leaves all further IRQs disabled | |
| 9 * for the full execution duration of an IRQ handler. (IRQ handlers are | |
| 10 * really LISRs, but TI's GSM fw does not use Nucleus' LISR framework.) | |
| 11 */ | |
| 12 | |
| 13 .section iram.text,"ax",%progbits | |
| 14 .code 32 | |
| 15 | |
| 16 .globl _INT_IRQ | |
| 17 _INT_IRQ: | |
| 18 STMDB sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack | |
| 19 | |
| 20 /* | |
| 21 * Thanks to TI for discovering and documenting this apparent ARM7TDMI bug: | |
| 22 | |
| 23 BUG correction 1st part ------------------- | |
| 24 It looks like there is an issue with ARM7 IRQ masking in the CPSR register | |
| 25 which leads to crashes in Nucleus+ scheduler. | |
| 26 Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not | |
| 27 prevent from having an interrupt after the execution of the third line (I mean execution, not | |
| 28 fetch). | |
| 29 MRS a1,CPSR ; Pickup current CPSR | |
| 30 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value | |
| 31 MSR CPSR,a1 ; Lockout interrupts | |
| 32 * IRQ INTERRUPT ! * | |
| 33 Next instructions... | |
| 34 | |
| 35 SW workaround: | |
| 36 When a task is interrupted at this point an interrupted context is stored on its task and will | |
| 37 be resumed later on at the next instruction but to make a long story short it leads to some | |
| 38 problem as the OS does not expect to be interrupted there. | |
| 39 Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value | |
| 40 but that the IRQ is still triggered (has been hardwarewise requested during the instruction | |
| 41 exectution by the ARM7 core?) | |
| 42 */ | |
| 43 | |
| 44 MRS a1,spsr @ check for the IRQ bug: | |
| 45 TST a1,#0x80 @ if the I - flag is set, | |
| 46 BNE IRQBUG @ then postpone execution of this IRQ | |
| 47 /* Bug correction 1st part end --------------- */ | |
| 48 | |
| 49 SUB a4,lr,#4 @ Save IRQ's lr (return address) | |
| 50 BL TCT_Interrupt_Context_Save @ Call context save routine | |
| 51 | |
| 52 BL IQ_IRQ_isr @ Call int. service routine | |
| 53 | |
| 54 /* IRQ interrupt processing is complete. Restore context- Never | |
| 55 returns! */ | |
| 56 B TCT_Interrupt_Context_Restore | |
| 57 | |
| 58 /* BUG correction 2nd part ------------------ */ | |
| 59 IRQBUG: LDMFD sp!,{a1-a4} @ return from interrupt | |
| 60 SUBS pc,r14,#4 | |
| 61 /* BUG correction 2nd part end -------------- */ | |
| 62 | |
| 63 .globl _INT_FIQ | |
| 64 _INT_FIQ: | |
| 65 STMDB sp!,{a1-a4} @ Save a1-a4 on temporary FIQ stack | |
| 66 SUB a4,lr,#4 @ Save FIQ's lr (return address) | |
| 67 BL TCT_Interrupt_Context_Save @ Call context save routine | |
| 68 | |
| 69 BL IQ_FIQ_isr @ Call the FIQ ISR | |
| 70 | |
| 71 /* FIQ interrupt processing is complete. Restore context- Never | |
| 72 returns! */ | |
| 73 B TCT_Interrupt_Context_Restore |